Suzero. X8664. NaCl Sandboxing.

src/IceTargetLoweringX8664Traits.h

 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 283 matching lines @@
     SSE4_1,
     End
   };
 
   static const char *TargetName;
   static constexpr Type WordType = IceType_i64;
 
   static IceString getRegName(int32_t RegNum) {
     static const char *const RegNames[RegisterSet::Reg_NUM] = {
 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
-          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
-          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
+          sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,      \
+          is16To8, isTrunc8Rcvr, isAhRcvr, aliases)                            \
   name,
         REGX8664_TABLE
 #undef X
     };
     assert(RegNum >= 0);
     assert(RegNum < RegisterSet::Reg_NUM);
     return RegNames[RegNum];
   }
 
   static GPRRegister getEncodedGPR(int32_t RegNum) {
     static const GPRRegister GPRRegs[RegisterSet::Reg_NUM] = {
 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
-          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
-          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
+          sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,      \
+          is16To8, isTrunc8Rcvr, isAhRcvr, aliases)                            \
   GPRRegister(isGPR ? encode : GPRRegister::Encoded_Not_GPR),
         REGX8664_TABLE
 #undef X
     };
     assert(RegNum >= 0);
     assert(RegNum < RegisterSet::Reg_NUM);
     assert(GPRRegs[RegNum] != GPRRegister::Encoded_Not_GPR);
     return GPRRegs[RegNum];
   }
 
   static ByteRegister getEncodedByteReg(int32_t RegNum) {
     static const ByteRegister ByteRegs[RegisterSet::Reg_NUM] = {
 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
-          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
-          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
+          sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,      \
+          is16To8, isTrunc8Rcvr, isAhRcvr, aliases)                            \
   ByteRegister(is8 ? encode : ByteRegister::Encoded_Not_ByteReg),
         REGX8664_TABLE
 #undef X
     };
     assert(RegNum >= 0);
     assert(RegNum < RegisterSet::Reg_NUM);
     assert(ByteRegs[RegNum] != ByteRegister::Encoded_Not_ByteReg);
     return ByteRegs[RegNum];
   }
 
   static XmmRegister getEncodedXmm(int32_t RegNum) {
     static const XmmRegister XmmRegs[RegisterSet::Reg_NUM] = {
 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
-          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
-          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
+          sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,      \
+          is16To8, isTrunc8Rcvr, isAhRcvr, aliases)                            \
   XmmRegister(isXmm ? encode : XmmRegister::Encoded_Not_Xmm),
         REGX8664_TABLE
 #undef X
     };
     assert(RegNum >= 0);
     assert(RegNum < RegisterSet::Reg_NUM);
     assert(XmmRegs[RegNum] != XmmRegister::Encoded_Not_Xmm);
     return XmmRegs[RegNum];
   }
 
   static uint32_t getEncoding(int32_t RegNum) {
     static const uint32_t Encoding[RegisterSet::Reg_NUM] = {
 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
-          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
-          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
+          sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,      \
+          is16To8, isTrunc8Rcvr, isAhRcvr, aliases)                            \
   encode,
         REGX8664_TABLE
 #undef X
     };
     assert(RegNum >= 0);
     assert(RegNum < RegisterSet::Reg_NUM);
     return Encoding[RegNum];
   }
 
   static inline int32_t getBaseReg(int32_t RegNum) {
     static const int32_t BaseRegs[RegisterSet::Reg_NUM] = {
 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
-          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
-          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
-  RegisterSet::base,
+          sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,      \
+          is16To8, isTrunc8Rcvr, isAhRcvr, aliases)                            \
+  encode,
         REGX8664_TABLE
 #undef X
     };
     assert(RegNum >= 0);
     assert(RegNum < RegisterSet::Reg_NUM);
     return BaseRegs[RegNum];
   }
 
 private:
   static int32_t getFirstGprForType(Type Ty) {
@@ skipping 31 matching lines @@
     assert(RegNum != RegisterSet::Reg_bh);
     assert(RegNum != RegisterSet::Reg_ch);
     assert(RegNum != RegisterSet::Reg_dh);
 
     const int32_t FirstGprForType = getFirstGprForType(Ty);
 
     switch (RegNum) {
     default:
       llvm::report_fatal_error("Unknown register.");
 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
-          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
-          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
+          sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,      \
+          is16To8, isTrunc8Rcvr, isAhRcvr, aliases)                            \
   case RegisterSet::val: {                                                     \
-    assert(isGPR);                                                             \
+    if (!isGPR)                                                                \
+      return RegisterSet::val;                                                 \
     assert((is64) || (is32) || (is16) || (is8) ||                              \
-           getBaseReg(RegisterSet::val) == RegisterSet::Reg_rsp);              \
+           getBaseReg(RegisterSet::val) == RegisterSet::Reg_rsp ||             \
+           getBaseReg(RegisterSet::val) == RegisterSet::Reg_rbp);              \
     constexpr int32_t FirstGprWithRegNumSize =                                 \
-        ((is64) || RegisterSet::val == RegisterSet::Reg_rsp)                   \
+        ((is64) || RegisterSet::val == RegisterSet::Reg_rsp ||                 \
+         RegisterSet::val == RegisterSet::Reg_rbp)                             \
             ? RegisterSet::Reg_rax                                             \
-            : (((is32) || RegisterSet::val == RegisterSet::Reg_esp)            \
+            : (((is32) || RegisterSet::val == RegisterSet::Reg_esp ||          \
+                RegisterSet::val == RegisterSet::Reg_ebp)                      \
                    ? RegisterSet::Reg_eax                                      \
-                   : (((is16) || RegisterSet::val == RegisterSet::Reg_sp)      \
+                   : (((is16) || RegisterSet::val == RegisterSet::Reg_sp ||    \
+                       RegisterSet::val == RegisterSet::Reg_bp)                \
                           ? RegisterSet::Reg_ax                                \
                           : RegisterSet::Reg_al));                             \
     const int32_t NewRegNum =                                                  \
         RegNum - FirstGprWithRegNumSize + FirstGprForType;                     \
     assert(getBaseReg(RegNum) == getBaseReg(NewRegNum) &&                      \
            "Error involving " #val);                                           \
     return NewRegNum;                                                          \
   }
       REGX8664_TABLE
 #undef X
     }
   }
 
 private:
   /// SizeOf is used to obtain the size of an initializer list as a constexpr
   /// expression. This is only needed until our C++ library is updated to
   /// C++ 14 -- which defines constexpr members to std::initializer_list.
   class SizeOf {
     SizeOf(const SizeOf &) = delete;
     SizeOf &operator=(const SizeOf &) = delete;
 
   public:
     constexpr SizeOf() : Size(0) {}
     template <typename... T>
     explicit constexpr SizeOf(T...)
-        : Size(__length<T...>::value) {}
+        : Size(length<T...>::value) {}
     constexpr SizeT size() const { return Size; }
 
   private:
-    template <typename T, typename... U> struct __length {
-      static constexpr std::size_t value = 1 + __length<U...>::value;
+    template <typename T, typename... U> struct length {
+      static constexpr std::size_t value = 1 + length<U...>::value;
     };
 
-    template <typename T> struct __length<T> {
+    template <typename T> struct length<T> {
       static constexpr std::size_t value = 1;
     };
 
     const std::size_t Size;
   };
 
 public:
   static void initRegisterSet(
+      const ::Ice::ClFlags &Flags,
       std::array<llvm::SmallBitVector, RCX86_NUM> *TypeToRegisterSet,
       std::array<llvm::SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases,
       llvm::SmallBitVector *ScratchRegs) {
     llvm::SmallBitVector IntegerRegistersI64(RegisterSet::Reg_NUM);
     llvm::SmallBitVector IntegerRegistersI32(RegisterSet::Reg_NUM);
     llvm::SmallBitVector IntegerRegistersI16(RegisterSet::Reg_NUM);
     llvm::SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM);
     llvm::SmallBitVector FloatRegisters(RegisterSet::Reg_NUM);
     llvm::SmallBitVector VectorRegisters(RegisterSet::Reg_NUM);
     llvm::SmallBitVector Trunc64To8Registers(RegisterSet::Reg_NUM);
     llvm::SmallBitVector Trunc32To8Registers(RegisterSet::Reg_NUM);
     llvm::SmallBitVector Trunc16To8Registers(RegisterSet::Reg_NUM);
     llvm::SmallBitVector Trunc8RcvrRegisters(RegisterSet::Reg_NUM);
     llvm::SmallBitVector AhRcvrRegisters(RegisterSet::Reg_NUM);
     llvm::SmallBitVector InvalidRegisters(RegisterSet::Reg_NUM);
     ScratchRegs->resize(RegisterSet::Reg_NUM);
 
     static constexpr struct {
       uint16_t Val;
+      unsigned IsReservedWhenSandboxing : 1;
       unsigned Is64 : 1;
       unsigned Is32 : 1;
       unsigned Is16 : 1;
       unsigned Is8 : 1;
       unsigned IsXmm : 1;
       unsigned Is64To8 : 1;
       unsigned Is32To8 : 1;
       unsigned Is16To8 : 1;
       unsigned IsTrunc8Rcvr : 1;
       unsigned IsAhRcvr : 1;
       unsigned Scratch : 1;
 #define NUM_ALIASES_BITS 2
       SizeT NumAliases : (NUM_ALIASES_BITS + 1);
       uint16_t Aliases[1 << NUM_ALIASES_BITS];
 #undef NUM_ALIASES_BITS
     } X8664RegTable[RegisterSet::Reg_NUM] = {
 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
-          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
-          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
+          sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,      \
+          is16To8, isTrunc8Rcvr, isAhRcvr, aliases)                            \
   {                                                                            \
-    RegisterSet::val, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, \
-        isTrunc8Rcvr, isAhRcvr, scratch, (SizeOf aliases).size(), aliases,     \
+    RegisterSet::val, sboxres, is64, is32, is16, is8, isXmm, is64To8, is32To8, \
+        is16To8, isTrunc8Rcvr, isAhRcvr, scratch, (SizeOf aliases).size(),     \
+        aliases,                                                               \
   }                                                                            \
   ,
         REGX8664_TABLE
 #undef X
     };
 
+    const bool NeedSandboxing = Flags.getUseSandboxing();
     for (SizeT ii = 0; ii < llvm::array_lengthof(X8664RegTable); ++ii) {
       const auto &Entry = X8664RegTable[ii];
+      // Even though the register is disabled for register allocation, it might
+      // still be used by the Target Lowering (e.g., base pointer), so the
+      // register talias table still needs to be defined.
+      (*RegisterAliases)[Entry.Val].resize(RegisterSet::Reg_NUM);
+      for (int J = 0; J < Entry.NumAliases; ++J) {
+        SizeT Alias = Entry.Aliases[J];
+        assert(!(*RegisterAliases)[Entry.Val][Alias] && "Duplicate alias");
+        (*RegisterAliases)[Entry.Val].set(Alias);
+      }
+
+      (*RegisterAliases)[Entry.Val].set(Entry.Val);
+      const bool DisabledRegister =
+          NeedSandboxing && Entry.IsReservedWhenSandboxing;
+      if (DisabledRegister) {
+        continue;
+      }
       (IntegerRegistersI64)[Entry.Val] = Entry.Is64;
       (IntegerRegistersI32)[Entry.Val] = Entry.Is32;
       (IntegerRegistersI16)[Entry.Val] = Entry.Is16;
       (IntegerRegistersI8)[Entry.Val] = Entry.Is8;
       (FloatRegisters)[Entry.Val] = Entry.IsXmm;
       (VectorRegisters)[Entry.Val] = Entry.IsXmm;
       (Trunc64To8Registers)[Entry.Val] = Entry.Is64To8;
       (Trunc32To8Registers)[Entry.Val] = Entry.Is32To8;
       (Trunc16To8Registers)[Entry.Val] = Entry.Is16To8;
       (Trunc8RcvrRegisters)[Entry.Val] = Entry.IsTrunc8Rcvr;
       (AhRcvrRegisters)[Entry.Val] = Entry.IsAhRcvr;
-      (*RegisterAliases)[Entry.Val].resize(RegisterSet::Reg_NUM);
-      for (int J = 0; J < Entry.NumAliases; ++J) {
-        SizeT Alias = Entry.Aliases[J];
-        assert(!(*RegisterAliases)[Entry.Val][Alias] && "Duplicate alias");
-        (*RegisterAliases)[Entry.Val].set(Alias);
-      }
-      (*RegisterAliases)[Entry.Val].set(Entry.Val);
       (*ScratchRegs)[Entry.Val] = Entry.Scratch;
     }
 
     (*TypeToRegisterSet)[RC_void] = InvalidRegisters;
     (*TypeToRegisterSet)[RC_i1] = IntegerRegistersI8;
     (*TypeToRegisterSet)[RC_i8] = IntegerRegistersI8;
     (*TypeToRegisterSet)[RC_i16] = IntegerRegistersI16;
     (*TypeToRegisterSet)[RC_i32] = IntegerRegistersI32;
     (*TypeToRegisterSet)[RC_i64] = IntegerRegistersI64;
     (*TypeToRegisterSet)[RC_f32] = FloatRegisters;
     (*TypeToRegisterSet)[RC_f64] = FloatRegisters;
     (*TypeToRegisterSet)[RC_v4i1] = VectorRegisters;
     (*TypeToRegisterSet)[RC_v8i1] = VectorRegisters;
     (*TypeToRegisterSet)[RC_v16i1] = VectorRegisters;
     (*TypeToRegisterSet)[RC_v16i8] = VectorRegisters;
     (*TypeToRegisterSet)[RC_v8i16] = VectorRegisters;
     (*TypeToRegisterSet)[RC_v4i32] = VectorRegisters;
     (*TypeToRegisterSet)[RC_v4f32] = VectorRegisters;
     (*TypeToRegisterSet)[RCX86_Is64To8] = Trunc64To8Registers;
     (*TypeToRegisterSet)[RCX86_Is32To8] = Trunc32To8Registers;
     (*TypeToRegisterSet)[RCX86_Is16To8] = Trunc16To8Registers;
     (*TypeToRegisterSet)[RCX86_IsTrunc8Rcvr] = Trunc8RcvrRegisters;
     (*TypeToRegisterSet)[RCX86_IsAhRcvr] = AhRcvrRegisters;
   }
 
   static llvm::SmallBitVector
-  getRegisterSet(TargetLowering::RegSetMask Include,
+  getRegisterSet(const ::Ice::ClFlags &Flags,
+                 TargetLowering::RegSetMask Include,
                  TargetLowering::RegSetMask Exclude) {
     llvm::SmallBitVector Registers(RegisterSet::Reg_NUM);
 
+    const bool NeedSandboxing = Flags.getUseSandboxing();
 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
-          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
-          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
-  if (scratch && (Include & ::Ice::TargetLowering::RegSet_CallerSave))         \
-    Registers[RegisterSet::val] = true;                                        \
-  if (preserved && (Include & ::Ice::TargetLowering::RegSet_CalleeSave))       \
-    Registers[RegisterSet::val] = true;                                        \
-  if (stackptr && (Include & ::Ice::TargetLowering::RegSet_StackPointer))      \
-    Registers[RegisterSet::val] = true;                                        \
-  if (frameptr && (Include & ::Ice::TargetLowering::RegSet_FramePointer))      \
-    Registers[RegisterSet::val] = true;                                        \
-  if (scratch && (Exclude & ::Ice::TargetLowering::RegSet_CallerSave))         \
-    Registers[RegisterSet::val] = false;                                       \
-  if (preserved && (Exclude & ::Ice::TargetLowering::RegSet_CalleeSave))       \
-    Registers[RegisterSet::val] = false;                                       \
-  if (stackptr && (Exclude & ::Ice::TargetLowering::RegSet_StackPointer))      \
-    Registers[RegisterSet::val] = false;                                       \
-  if (frameptr && (Exclude & ::Ice::TargetLowering::RegSet_FramePointer))      \
-    Registers[RegisterSet::val] = false;
+          sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,      \
+          is16To8, isTrunc8Rcvr, isAhRcvr, aliases)                            \
+  if (!NeedSandboxing || !(sboxres)) {                                         \
+    if (scratch && (Include & ::Ice::TargetLowering::RegSet_CallerSave))       \
+      Registers[RegisterSet::val] = true;                                      \
+    if (preserved && (Include & ::Ice::TargetLowering::RegSet_CalleeSave))     \
+      Registers[RegisterSet::val] = true;                                      \
+    if (stackptr && (Include & ::Ice::TargetLowering::RegSet_StackPointer))    \
+      Registers[RegisterSet::val] = true;                                      \
+    if (frameptr && (Include & ::Ice::TargetLowering::RegSet_FramePointer))    \
+      Registers[RegisterSet::val] = true;                                      \
+    if (scratch && (Exclude & ::Ice::TargetLowering::RegSet_CallerSave))       \
+      Registers[RegisterSet::val] = false;                                     \
+    if (preserved && (Exclude & ::Ice::TargetLowering::RegSet_CalleeSave))     \
+      Registers[RegisterSet::val] = false;                                     \
+    if (stackptr && (Exclude & ::Ice::TargetLowering::RegSet_StackPointer))    \
+      Registers[RegisterSet::val] = false;                                     \
+    if (frameptr && (Exclude & ::Ice::TargetLowering::RegSet_FramePointer))    \
+      Registers[RegisterSet::val] = false;                                     \
+  }
 
     REGX8664_TABLE
 
 #undef X
 
     return Registers;
   }
 
   static void
   makeRandomRegisterPermutation(GlobalContext *Ctx, Cfg *Func,
                                 llvm::SmallVectorImpl<int32_t> &Permutation,
                                 const llvm::SmallBitVector &ExcludeRegisters,
                                 uint64_t Salt) {
     // TODO(stichnot): Declaring Permutation this way loses type/size
     // information. Fix this in conjunction with the caller-side TODO.
     assert(Permutation.size() >= RegisterSet::Reg_NUM);
     // Expected upper bound on the number of registers in a single equivalence
     // class.  For x86-64, this would comprise the 16 XMM registers. This is
     // for performance, not correctness.
     static const unsigned MaxEquivalenceClassSize = 8;
     using RegisterList = llvm::SmallVector<int32_t, MaxEquivalenceClassSize>;
     using EquivalenceClassMap = std::map<uint32_t, RegisterList>;
     EquivalenceClassMap EquivalenceClasses;
     SizeT NumShuffled = 0, NumPreserved = 0;
 
 // Build up the equivalence classes of registers by looking at the register
 // properties as well as whether the registers should be explicitly excluded
 // from shuffling.
 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
-          isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
-          isTrunc8Rcvr, isAhRcvr, aliases)                                     \
+          sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,      \
+          is16To8, isTrunc8Rcvr, isAhRcvr, aliases)                            \
   if (ExcludeRegisters[RegisterSet::val]) {                                    \
     /* val stays the same in the resulting permutation. */                     \
     Permutation[RegisterSet::val] = RegisterSet::val;                          \
     ++NumPreserved;                                                            \
   } else {                                                                     \
     uint32_t AttrKey = 0;                                                      \
     uint32_t Index = 0;                                                        \
     /* Combine relevant attributes into an equivalence class key. */           \
     Index |= (scratch << (AttrKey++));                                         \
     Index |= (preserved << (AttrKey++));                                       \
@@ skipping 193 matching lines @@
     X86OperandMem() = delete;
     X86OperandMem(const X86OperandMem &) = delete;
     X86OperandMem &operator=(const X86OperandMem &) = delete;
 
   public:
     enum SegmentRegisters { DefaultSegment = -1, SegReg_NUM };
     static X86OperandMem *
     create(Cfg *Func, Type Ty, Variable *Base, Constant *Offset,
            Variable *Index = nullptr, uint16_t Shift = 0,
            SegmentRegisters SegmentRegister = DefaultSegment,
-           bool IsPIC = false) {
+           bool IsRebased = false) {
       assert(SegmentRegister == DefaultSegment);
       (void)SegmentRegister;
       return new (Func->allocate<X86OperandMem>())
-          X86OperandMem(Func, Ty, Base, Offset, Index, Shift, IsPIC);
+          X86OperandMem(Func, Ty, Base, Offset, Index, Shift, IsRebased);
+    }
+    static X86OperandMem *create(Cfg *Func, Type Ty, Variable *Base,
+                                 Constant *Offset, bool IsRebased) {
+      constexpr Variable *NoIndex = nullptr;
+      constexpr uint16_t NoShift = 0;
+      return new (Func->allocate<X86OperandMem>())
+          X86OperandMem(Func, Ty, Base, Offset, NoIndex, NoShift, IsRebased);
     }
     Variable *getBase() const { return Base; }
     Constant *getOffset() const { return Offset; }
     Variable *getIndex() const { return Index; }
     uint16_t getShift() const { return Shift; }
     SegmentRegisters getSegmentRegister() const { return DefaultSegment; }
     void emitSegmentOverride(Assembler *) const {}
-    void setIsPIC() { IsPIC = true; }
-    bool getIsPIC() const { return IsPIC; }
-    Address toAsmAddress(Assembler *Asm,
-                         const Ice::TargetLowering *Target) const;
+    bool getIsRebased() const { return IsRebased; }
+    Address toAsmAddress(Assembler *Asm, const Ice::TargetLowering *Target,
+                         bool IsLeaAddr = false) const;
 
     void emit(const Cfg *Func) const override;
     using X86Operand::dump;
     void dump(const Cfg *Func, Ostream &Str) const override;
 
     static bool classof(const Operand *Operand) {
       return Operand->getKind() == static_cast<OperandKind>(kMem);
     }
 
     void setRandomized(bool R) { Randomized = R; }
 
     bool getRandomized() const { return Randomized; }
 
   private:
     X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset,
-                  Variable *Index, uint16_t Shift, bool IsPIC);
+                  Variable *Index, uint16_t Shift, bool IsRebased);
 
-    Variable *Base;
-    Constant *Offset;
-    Variable *Index;
-    uint16_t Shift;
-    bool IsPIC;
+    Variable *const Base;
+    Constant *const Offset;
+    Variable *const Index;
+    const uint16_t Shift;
+    const bool IsRebased;
     /// A flag to show if this memory operand is a randomized one. Randomized
     /// memory operands are generated in
     /// TargetX86Base::randomizeOrPoolImmediate()
     bool Randomized = false;
   };
 
   /// VariableSplit is a way to treat an f64 memory location as a pair of i32
   /// locations (Low and High). This is needed for some cases of the Bitcast
   /// instruction. Since it's not possible for integer registers to access the
   /// XMM registers and vice versa, the lowering forces the f64 to be spilled to
@@ skipping 86 matching lines @@
     const char *FldString;   // s, l, or <blank>
   } TypeAttributes[];
 };
 
 using Traits = ::Ice::X8664::TargetX8664Traits;
 } // end of namespace X8664
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H