Suzero. X8664. NaCl Sandboxing.

src/IceAssemblerX86Base.h

 //===- subzero/src/IceAssemblerX86Base.h - base x86 assembler -*- C++ -*---===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 26 matching lines @@
 #endif
 
 namespace X86NAMESPACE {
 
 template <typename TraitsType>
 class AssemblerX86Base : public ::Ice::Assembler {
   AssemblerX86Base(const AssemblerX86Base &) = delete;
   AssemblerX86Base &operator=(const AssemblerX86Base &) = delete;
 
 protected:
-  explicit AssemblerX86Base(bool use_far_branches = false)
-      : Assembler(Traits::AsmKind) {
-    // This mode is only needed and implemented for MIPS and ARM.
-    assert(!use_far_branches);
-    (void)use_far_branches;
+  explicit AssemblerX86Base(bool EmitAddrSizeOverridePrefix = Traits::Is64Bit)
+      : Assembler(Traits::AsmKind),
+        EmitAddrSizeOverridePrefix(EmitAddrSizeOverridePrefix) {
+    assert(Traits::Is64Bit || !EmitAddrSizeOverridePrefix);
   }
 
 public:
   using Traits = TraitsType;
   using Address = typename Traits::Address;
   using ByteRegister = typename Traits::ByteRegister;
   using BrCond = typename Traits::Cond::BrCond;
   using CmppsCond = typename Traits::Cond::CmppsCond;
   using GPRRegister = typename Traits::GPRRegister;
   using Operand = typename Traits::Operand;
@@ skipping 219 matching lines @@
    * Emit Machine Instructions.
    */
   void call(GPRRegister reg);
   void call(const Address &address);
   void call(const ConstantRelocatable *label); // not testable.
   void call(const Immediate &abs_address);
 
   static const intptr_t kCallExternalLabelSize = 5;
 
   void pushl(GPRRegister reg);
+  void pushl(const Immediate &Imm);
+  void pushl(const ConstantRelocatable *Label);
 
   void popl(GPRRegister reg);
   void popl(const Address &address);
 
   template <typename T = Traits,
             typename = typename std::enable_if<T::HasPusha>::type>
   void pushal();
   template <typename T = Traits,
             typename = typename std::enable_if<T::HasPopa>::type>
   void popal();
@@ skipping 403 matching lines @@
   void bind(Label *label);
 
   intptr_t CodeSize() const { return Buffer.size(); }
 
 protected:
   inline void emitUint8(uint8_t value);
 
 private:
   ENABLE_MAKE_UNIQUE;
 
+  // EmidAddrSizeOverridePrefix directs the emission of the 0x67 prefix to
+  // force 32-bit registers when accessing memory. This is only used in native
+  // 64-bit.
+  const bool EmitAddrSizeOverridePrefix;
+
   static constexpr Type RexTypeIrrelevant = IceType_i32;
   static constexpr Type RexTypeForceRexW = IceType_i64;
   static constexpr GPRRegister RexRegIrrelevant =
       Traits::GPRRegister::Encoded_Reg_eax;
 
   inline void emitInt16(int16_t value);
   inline void emitInt32(int32_t value);
   inline void emitRegisterOperand(int rm, int reg);
   template <typename RegType, typename RmType>
   inline void emitXmmRegisterOperand(RegType reg, RmType rm);
@@ skipping 15 matching lines @@
 
   using LabelVector = std::vector<Label *>;
   // A vector of pool-allocated x86 labels for CFG nodes.
   LabelVector CfgNodeLabels;
   // A vector of pool-allocated x86 labels for Local labels.
   LabelVector LocalLabels;
 
   Label *getOrCreateLabel(SizeT Number, LabelVector &Labels);
 
   void emitAddrSizeOverridePrefix() {
-    if (!Traits::Is64Bit) {
+    if (!Traits::Is64Bit || !EmitAddrSizeOverridePrefix) {
       return;
     }
     static constexpr uint8_t AddrSizeOverridePrefix = 0x67;
     emitUint8(AddrSizeOverridePrefix);
   }
 
   // The arith_int() methods factor out the commonality between the encodings
   // of add(), Or(), adc(), sbb(), And(), sub(), Xor(), and cmp(). The Tag
   // parameter is statically asserted to be less than 8.
   template <uint32_t Tag>
@@ skipping 149 matching lines @@
   emitUint8(0x66);
 }
 
 } // end of namespace X86NAMESPACE
 
 } // end of namespace Ice
 
 #include "IceAssemblerX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICEASSEMBLERX86BASE_H