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Side by Side Diff: src/IceTargetLoweringX8632.cpp

Issue 1559243002: Suzero. X8664. NaCl Sandboxing. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: make format Created 4 years, 11 months ago
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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
(...skipping 112 matching lines...) Expand 10 before | Expand all | Expand 10 after
123 TargetX86Base<X8632::Traits>::Traits::FK_Abs; 123 TargetX86Base<X8632::Traits>::Traits::FK_Abs;
124 124
125 //------------------------------------------------------------------------------ 125 //------------------------------------------------------------------------------
126 // __ ______ __ __ ______ ______ __ __ __ ______ 126 // __ ______ __ __ ______ ______ __ __ __ ______
127 // /\ \ /\ __ \/\ \ _ \ \/\ ___\/\ == \/\ \/\ "-.\ \/\ ___\ 127 // /\ \ /\ __ \/\ \ _ \ \/\ ___\/\ == \/\ \/\ "-.\ \/\ ___\
128 // \ \ \___\ \ \/\ \ \ \/ ".\ \ \ __\\ \ __<\ \ \ \ \-. \ \ \__ \ 128 // \ \ \___\ \ \/\ \ \ \/ ".\ \ \ __\\ \ __<\ \ \ \ \-. \ \ \__ \
129 // \ \_____\ \_____\ \__/".~\_\ \_____\ \_\ \_\ \_\ \_\\"\_\ \_____\ 129 // \ \_____\ \_____\ \__/".~\_\ \_____\ \_\ \_\ \_\ \_\\"\_\ \_____\
130 // \/_____/\/_____/\/_/ \/_/\/_____/\/_/ /_/\/_/\/_/ \/_/\/_____/ 130 // \/_____/\/_____/\/_/ \/_/\/_____/\/_/ /_/\/_/\/_/ \/_/\/_____/
131 // 131 //
132 //------------------------------------------------------------------------------ 132 //------------------------------------------------------------------------------
133 void TargetX8632::_add_sp(Operand *Adjustment) {
134 Variable *esp = getPhysicalRegister(Traits::RegisterSet::Reg_esp);
135 _add(esp, Adjustment);
136 }
137
138 void TargetX8632::_mov_sp(Operand *NewValue) {
139 Variable *esp = getPhysicalRegister(Traits::RegisterSet::Reg_esp);
140 _redefined(_mov(esp, NewValue));
141 }
142
143 void TargetX8632::_sub_sp(Operand *Adjustment) {
144 Variable *esp = getPhysicalRegister(Traits::RegisterSet::Reg_esp);
145 _sub(esp, Adjustment);
146 }
147
148 void TargetX8632::lowerIndirectJump(Variable *JumpTarget) {
149 if (NeedSandboxing) {
150 _bundle_lock();
151 const SizeT BundleSize =
152 1 << Func->getAssembler<>()->getBundleAlignLog2Bytes();
153 _and(JumpTarget, Ctx->getConstantInt32(~(BundleSize - 1)));
154 }
155 _jmp(JumpTarget);
156 if (NeedSandboxing)
157 _bundle_unlock();
158 }
159
133 void TargetX8632::lowerCall(const InstCall *Instr) { 160 void TargetX8632::lowerCall(const InstCall *Instr) {
134 // x86-32 calling convention: 161 // x86-32 calling convention:
135 // 162 //
136 // * At the point before the call, the stack must be aligned to 16 bytes. 163 // * At the point before the call, the stack must be aligned to 16 bytes.
137 // 164 //
138 // * The first four arguments of vector type, regardless of their position 165 // * The first four arguments of vector type, regardless of their position
139 // relative to the other arguments in the argument list, are placed in 166 // relative to the other arguments in the argument list, are placed in
140 // registers xmm0 - xmm3. 167 // registers xmm0 - xmm3.
141 // 168 //
142 // * Other arguments are pushed onto the stack in right-to-left order, such 169 // * Other arguments are pushed onto the stack in right-to-left order, such
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245 case IceType_v16i8: 272 case IceType_v16i8:
246 case IceType_v8i16: 273 case IceType_v8i16:
247 case IceType_v4i32: 274 case IceType_v4i32:
248 case IceType_v4f32: 275 case IceType_v4f32:
249 ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_xmm0); 276 ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_xmm0);
250 break; 277 break;
251 } 278 }
252 } 279 }
253 Operand *CallTarget = 280 Operand *CallTarget =
254 legalize(Instr->getCallTarget(), Legal_Reg | Legal_Imm | Legal_AddrAbs); 281 legalize(Instr->getCallTarget(), Legal_Reg | Legal_Imm | Legal_AddrAbs);
255 const bool NeedSandboxing = Ctx->getFlags().getUseSandboxing();
256 if (NeedSandboxing) { 282 if (NeedSandboxing) {
257 if (llvm::isa<Constant>(CallTarget)) { 283 if (llvm::isa<Constant>(CallTarget)) {
258 _bundle_lock(InstBundleLock::Opt_AlignToEnd); 284 _bundle_lock(InstBundleLock::Opt_AlignToEnd);
259 } else { 285 } else {
260 Variable *CallTargetVar = nullptr; 286 Variable *CallTargetVar = nullptr;
261 _mov(CallTargetVar, CallTarget); 287 _mov(CallTargetVar, CallTarget);
262 _bundle_lock(InstBundleLock::Opt_AlignToEnd); 288 _bundle_lock(InstBundleLock::Opt_AlignToEnd);
263 const SizeT BundleSize = 289 const SizeT BundleSize =
264 1 << Func->getAssembler<>()->getBundleAlignLog2Bytes(); 290 1 << Func->getAssembler<>()->getBundleAlignLog2Bytes();
265 _and(CallTargetVar, Ctx->getConstantInt32(~(BundleSize - 1))); 291 _and(CallTargetVar, Ctx->getConstantInt32(~(BundleSize - 1)));
(...skipping 446 matching lines...) Expand 10 before | Expand all | Expand 10 after
712 for (SizeT i = 0; i < Popped.size(); ++i) { 738 for (SizeT i = 0; i < Popped.size(); ++i) {
713 SizeT j = Popped.size() - i - 1; 739 SizeT j = Popped.size() - i - 1;
714 SizeT Canonical = Traits::getBaseReg(j); 740 SizeT Canonical = Traits::getBaseReg(j);
715 if (j == Traits::RegisterSet::Reg_ebp && IsEbpBasedFrame) 741 if (j == Traits::RegisterSet::Reg_ebp && IsEbpBasedFrame)
716 continue; 742 continue;
717 if (Popped[j]) { 743 if (Popped[j]) {
718 _pop(getPhysicalRegister(Canonical)); 744 _pop(getPhysicalRegister(Canonical));
719 } 745 }
720 } 746 }
721 747
722 if (!Ctx->getFlags().getUseSandboxing()) 748 if (!NeedSandboxing)
723 return; 749 return;
724 // Change the original ret instruction into a sandboxed return sequence. 750 // Change the original ret instruction into a sandboxed return sequence.
725 // t:ecx = pop 751 // t:ecx = pop
726 // bundle_lock 752 // bundle_lock
727 // and t, ~31 753 // and t, ~31
728 // jmp *t 754 // jmp *t
729 // bundle_unlock 755 // bundle_unlock
730 // FakeUse <original_ret_operand> 756 // FakeUse <original_ret_operand>
731 Variable *T_ecx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ecx); 757 Variable *T_ecx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ecx);
732 _pop(T_ecx); 758 _pop(T_ecx);
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1059 #define X(tag, sizeLog2, align, elts, elty, str) \ 1085 #define X(tag, sizeLog2, align, elts, elty, str) \
1060 static_assert(_table1_##tag == _table2_##tag, \ 1086 static_assert(_table1_##tag == _table2_##tag, \
1061 "Inconsistency between ICETYPEX8632_TABLE and ICETYPE_TABLE"); 1087 "Inconsistency between ICETYPEX8632_TABLE and ICETYPE_TABLE");
1062 ICETYPE_TABLE 1088 ICETYPE_TABLE
1063 #undef X 1089 #undef X
1064 } // end of namespace dummy3 1090 } // end of namespace dummy3
1065 } // end of anonymous namespace 1091 } // end of anonymous namespace
1066 1092
1067 } // end of namespace X8632 1093 } // end of namespace X8632
1068 } // end of namespace Ice 1094 } // end of namespace Ice
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