Index: src/interpreter/bytecodes.cc |
diff --git a/src/interpreter/bytecodes.cc b/src/interpreter/bytecodes.cc |
index 986e3d012e6c5a4cc34ae543eeac0db6276fb2d0..b7d044ac39aae3e1149d081f5d111d91e75fac55 100644 |
--- a/src/interpreter/bytecodes.cc |
+++ b/src/interpreter/bytecodes.cc |
@@ -273,6 +273,18 @@ std::ostream& Bytecodes::Decode(std::ostream& os, const uint8_t* bytecode_start, |
} |
break; |
} |
+ case interpreter::OperandType::kReg16: { |
+ Register reg = |
+ Register::FromWideOperand(ReadUnalignedUInt16(operand_start)); |
+ if (reg.is_parameter()) { |
+ int parameter_index = reg.ToParameterIndex(parameter_count); |
+ DCHECK_NE(parameter_index, 0); |
+ os << "a" << parameter_index - 1; |
+ } else { |
+ os << "r" << reg.index(); |
+ } |
+ break; |
+ } |
case interpreter::OperandType::kNone: |
UNREACHABLE(); |
break; |
@@ -322,7 +334,7 @@ Register Register::FromParameterIndex(int index, int parameter_count) { |
DCHECK_LE(parameter_count, kMaxParameterIndex + 1); |
int register_index = kLastParamRegisterIndex - parameter_count + index + 1; |
DCHECK_LT(register_index, 0); |
- DCHECK_GE(register_index, Register::kMinRegisterIndex); |
+ DCHECK_GE(register_index, kMinInt8); |
return Register(register_index); |
} |
@@ -364,7 +376,11 @@ bool Register::is_new_target() const { |
int Register::MaxParameterIndex() { return kMaxParameterIndex; } |
-uint8_t Register::ToOperand() const { return static_cast<uint8_t>(-index_); } |
+uint8_t Register::ToOperand() const { |
+ DCHECK_GE(index_, kMinInt8); |
+ DCHECK_LE(index_, kMaxInt8); |
+ return static_cast<uint8_t>(-index_); |
+} |
Register Register::FromOperand(uint8_t operand) { |
@@ -372,6 +388,18 @@ Register Register::FromOperand(uint8_t operand) { |
} |
+uint16_t Register::ToWideOperand() const { |
+ DCHECK_GE(index_, kMinInt16); |
+ DCHECK_LE(index_, kMaxInt16); |
+ return static_cast<uint16_t>(-index_); |
+} |
+ |
+ |
+Register Register::FromWideOperand(uint16_t operand) { |
+ return Register(-static_cast<int16_t>(operand)); |
+} |
+ |
+ |
bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, |
Register reg4, Register reg5) { |
if (reg1.index() + 1 != reg2.index()) { |