Subzero. ARM32. Materializes the register table.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 38 matching lines @@
 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
   return ::Ice::ARM32::TargetHeaderARM32::create(Ctx);
 }
 
 void staticInit() { ::Ice::ARM32::TargetARM32::staticInit(); }
 } // end of namespace ARM32
 
 namespace Ice {
 namespace ARM32 {
 
+// Defines the RegARM32::Table table with register information.
+constexpr RegARM32::TableType RegARM32::Table[];

[Karl, 2016/01/04 21:10:45]

Does this generate another copy for use below?

[John, 2016/01/04 21:45:12]

This is the definition for the array declaration. Without it, we get linker
errors. 

+
 namespace {
 
 // The following table summarizes the logic for lowering the icmp instruction
 // for i32 and narrower types. Each icmp condition has a clear mapping to an
 // ARM32 conditional move instruction.
 
 const struct TableIcmp32_ {
   CondARM32::Cond Mapping;
 } TableIcmp32[] = {
 #define X(val, is_signed, swapped64, C_32, C1_64, C2_64)                       \
@@ skipping 163 matching lines @@
 
 void TargetARM32::staticInit() {
   // Limit this size (or do all bitsets need to be the same width)???
   llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM);
   ScratchRegs.resize(RegARM32::Reg_NUM);
-#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
-          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
-  IntegerRegisters[RegARM32::val] = isInt;                                     \
-  I64PairRegisters[RegARM32::val] = isI64Pair;                                 \
-  Float32Registers[RegARM32::val] = isFP32;                                    \
-  Float64Registers[RegARM32::val] = isFP64;                                    \
-  VectorRegisters[RegARM32::val] = isVec128;                                   \
-  RegisterAliases[RegARM32::val].resize(RegARM32::Reg_NUM);                    \
-  for (SizeT RegAlias : alias_init) {                                          \
-    assert((!RegisterAliases[RegARM32::val][RegAlias] ||                       \
-            RegAlias != RegARM32::val) &&                                      \
-           "Duplicate alias for " #val);                                       \
-    RegisterAliases[RegARM32::val].set(RegAlias);                              \
-  }                                                                            \
-  RegisterAliases[RegARM32::val].set(RegARM32::val);                           \
-  ScratchRegs[RegARM32::val] = scratch;                                        \
-  if ((isInt) && (cc_arg) > 0) {                                               \
-    GPRArgInitializer[(cc_arg)-1] = RegARM32::val;                             \
-  } else if ((isI64Pair) && (cc_arg) > 0) {                                    \
-    I64ArgInitializer[(cc_arg)-1] = RegARM32::val;                             \
-  } else if ((isFP32) && (cc_arg) > 0) {                                       \
-    FP32ArgInitializer[(cc_arg)-1] = RegARM32::val;                            \
-  } else if ((isFP64) && (cc_arg) > 0) {                                       \
-    FP64ArgInitializer[(cc_arg)-1] = RegARM32::val;                            \
-  } else if ((isVec128) && (cc_arg) > 0) {                                     \
-    Vec128ArgInitializer[(cc_arg)-1] = RegARM32::val;                          \
+  for (int i = 0; i < RegARM32::Reg_NUM; ++i) {
+    const auto &Entry = RegARM32::Table[i];
+    IntegerRegisters[i] = Entry.IsInt;
+    I64PairRegisters[i] = Entry.IsI64Pair;
+    Float32Registers[i] = Entry.IsFP32;
+    Float64Registers[i] = Entry.IsFP64;
+    VectorRegisters[i] = Entry.IsVec128;
+    ScratchRegs[i] = Entry.Scratch;
+    RegisterAliases[i].resize(RegARM32::Reg_NUM);
+    for (int j = 0; j < Entry.NumAliases; ++j) {
+      assert(i == j || !RegisterAliases[i][Entry.Aliases[j]]);
+      RegisterAliases[i].set(Entry.Aliases[j]);
+    }
+    assert(RegisterAliases[i][i]);
+    if (Entry.CCArg <= 0) {
+      continue;
+    }
+    if (Entry.IsGPR) {
+      GPRArgInitializer[Entry.CCArg - 1] = i;
+    } else if (Entry.IsI64Pair) {
+      I64ArgInitializer[Entry.CCArg - 1] = i;
+    } else if (Entry.IsFP32) {
+      FP32ArgInitializer[Entry.CCArg - 1] = i;
+    } else if (Entry.IsFP64) {
+      FP64ArgInitializer[Entry.CCArg - 1] = i;
+    } else if (Entry.IsVec128) {
+      Vec128ArgInitializer[Entry.CCArg - 1] = i;
+    }
   }
-  REGARM32_TABLE;
-#undef X
   TypeToRegisterSet[IceType_void] = InvalidRegisters;
   TypeToRegisterSet[IceType_i1] = IntegerRegisters;
   TypeToRegisterSet[IceType_i8] = IntegerRegisters;
   TypeToRegisterSet[IceType_i16] = IntegerRegisters;
   TypeToRegisterSet[IceType_i32] = IntegerRegisters;
   TypeToRegisterSet[IceType_i64] = I64PairRegisters;
   TypeToRegisterSet[IceType_f32] = Float32Registers;
   TypeToRegisterSet[IceType_f64] = Float64Registers;
   TypeToRegisterSet[IceType_v4i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i1] = VectorRegisters;
@@ skipping 539 matching lines @@
   return ARM32_STACK_ALIGNMENT_BYTES;
 }
 
 bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) {
   if (auto *Br = llvm::dyn_cast<InstARM32Br>(I)) {
     return Br->optimizeBranch(NextNode);
   }
   return false;
 }
 
-const char *RegARM32::RegNames[] = {
-#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
-          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
-  name,
-    REGARM32_TABLE
-#undef X
-};
-
 IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const {
   assert(RegNum < RegARM32::Reg_NUM);
   (void)Ty;
-  return RegARM32::RegNames[RegNum];
+  return RegARM32::getRegName(RegNum);
 }
 
 Variable *TargetARM32::getPhysicalRegister(SizeT RegNum, Type Ty) {
   static const Type DefaultType[] = {
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   (isFP32)                                                                     \
       ? IceType_f32                                                            \
       : ((isFP64) ? IceType_f64 : ((isVec128 ? IceType_v4i32 : IceType_i32))),
       REGARM32_TABLE
@@ skipping 975 matching lines @@
     }
   }
   llvm::report_fatal_error("Unsupported operand type");
   return nullptr;
 }
 
 llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
                                                  RegSetMask Exclude) const {
   llvm::SmallBitVector Registers(RegARM32::Reg_NUM);
 
-#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
-          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
-  if (scratch && (Include & RegSet_CallerSave))                                \
-    Registers[RegARM32::val] = true;                                           \
-  if (preserved && (Include & RegSet_CalleeSave))                              \
-    Registers[RegARM32::val] = true;                                           \
-  if (stackptr && (Include & RegSet_StackPointer))                             \
-    Registers[RegARM32::val] = true;                                           \
-  if (frameptr && (Include & RegSet_FramePointer))                             \
-    Registers[RegARM32::val] = true;                                           \
-  if (scratch && (Exclude & RegSet_CallerSave))                                \
-    Registers[RegARM32::val] = false;                                          \
-  if (preserved && (Exclude & RegSet_CalleeSave))                              \
-    Registers[RegARM32::val] = false;                                          \
-  if (stackptr && (Exclude & RegSet_StackPointer))                             \
-    Registers[RegARM32::val] = false;                                          \
-  if (frameptr && (Exclude & RegSet_FramePointer))                             \
-    Registers[RegARM32::val] = false;
-
-  REGARM32_TABLE
-
-#undef X
+  for (int i = 0; i < RegARM32::Reg_NUM; ++i) {
+    const auto &Entry = RegARM32::Table[i];
+    if (Entry.Scratch && (Include & RegSet_CallerSave))
+      Registers[i] = true;
+    if (Entry.Preserved && (Include & RegSet_CalleeSave))
+      Registers[i] = true;
+    if (Entry.StackPtr && (Include & RegSet_StackPointer))
+      Registers[i] = true;
+    if (Entry.FramePtr && (Include & RegSet_FramePointer))
+      Registers[i] = true;
+    if (Entry.Scratch && (Exclude & RegSet_CallerSave))
+      Registers[i] = false;
+    if (Entry.Preserved && (Exclude & RegSet_CalleeSave))
+      Registers[i] = false;
+    if (Entry.StackPtr && (Exclude & RegSet_StackPointer))
+      Registers[i] = false;
+    if (Entry.FramePtr && (Exclude & RegSet_FramePointer))
+      Registers[i] = false;
+  }
 
   return Registers;
 }
 
 void TargetARM32::lowerAlloca(const InstAlloca *Inst) {
   // Conservatively require the stack to be aligned. Some stack adjustment
   // operations implemented below assume that the stack is aligned before the
   // alloca. All the alloca code ensures that the stack alignment is preserved
   // after the alloca. The stack alignment restriction can be relaxed in some
   // cases.
@@ skipping 4574 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 llvm::SmallBitVector TargetARM32::ScratchRegs;
 
 } // end of namespace ARM32
 } // end of namespace Ice