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1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===// | 1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===// |
2 // | 2 // |
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
4 // for details. All rights reserved. Use of this source code is governed by a | 4 // for details. All rights reserved. Use of this source code is governed by a |
5 // BSD-style license that can be found in the LICENSE file. | 5 // BSD-style license that can be found in the LICENSE file. |
6 // | 6 // |
7 // Modified by the Subzero authors. | 7 // Modified by the Subzero authors. |
8 // | 8 // |
9 //===----------------------------------------------------------------------===// | 9 //===----------------------------------------------------------------------===// |
10 // | 10 // |
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473 llvm::report_fatal_error(std::string(InstName) + ": " + RegName + | 473 llvm::report_fatal_error(std::string(InstName) + ": " + RegName + |
474 "=pc not allowed"); | 474 "=pc not allowed"); |
475 } | 475 } |
476 | 476 |
477 void verifyRegNotPcWhenSetFlags(IValueT Reg, bool SetFlags, | 477 void verifyRegNotPcWhenSetFlags(IValueT Reg, bool SetFlags, |
478 const char *InstName) { | 478 const char *InstName) { |
479 if (BuildDefs::minimal()) | 479 if (BuildDefs::minimal()) |
480 return; | 480 return; |
481 if (SetFlags && (Reg == RegARM32::Encoded_Reg_pc)) | 481 if (SetFlags && (Reg == RegARM32::Encoded_Reg_pc)) |
482 llvm::report_fatal_error(std::string(InstName) + ": " + | 482 llvm::report_fatal_error(std::string(InstName) + ": " + |
483 RegARM32::RegNames[Reg] + | 483 RegARM32::getRegName(Reg) + |
484 "=pc not allowed when CC=1"); | 484 "=pc not allowed when CC=1"); |
485 } | 485 } |
486 | 486 |
487 } // end of anonymous namespace | 487 } // end of anonymous namespace |
488 | 488 |
489 namespace Ice { | 489 namespace Ice { |
490 namespace ARM32 { | 490 namespace ARM32 { |
491 | 491 |
492 size_t MoveRelocatableFixup::emit(GlobalContext *Ctx, | 492 size_t MoveRelocatableFixup::emit(GlobalContext *Ctx, |
493 const Assembler &Asm) const { | 493 const Assembler &Asm) const { |
494 if (!BuildDefs::dump()) | 494 if (!BuildDefs::dump()) |
495 return InstARM32::InstSize; | 495 return InstARM32::InstSize; |
496 Ostream &Str = Ctx->getStrEmit(); | 496 Ostream &Str = Ctx->getStrEmit(); |
497 IValueT Inst = Asm.load<IValueT>(position()); | 497 IValueT Inst = Asm.load<IValueT>(position()); |
498 Str << "\t" | 498 Str << "\t" |
499 "mov" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "w" : "t") << "\t" | 499 "mov" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "w" : "t") << "\t" |
500 << RegARM32::RegNames[(Inst >> kRdShift) & 0xF] | 500 << RegARM32::getRegName((Inst >> kRdShift) & 0xF) |
501 << ", #:" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "lower" : "upper") | 501 << ", #:" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "lower" : "upper") |
502 << "16:" << symbol(Ctx) << "\t@ .word " | 502 << "16:" << symbol(Ctx) << "\t@ .word " |
503 << llvm::format_hex_no_prefix(Inst, 8) << "\n"; | 503 << llvm::format_hex_no_prefix(Inst, 8) << "\n"; |
504 return InstARM32::InstSize; | 504 return InstARM32::InstSize; |
505 } | 505 } |
506 | 506 |
507 MoveRelocatableFixup *AssemblerARM32::createMoveFixup(bool IsMovW, | 507 MoveRelocatableFixup *AssemblerARM32::createMoveFixup(bool IsMovW, |
508 const Constant *Value) { | 508 const Constant *Value) { |
509 MoveRelocatableFixup *F = | 509 MoveRelocatableFixup *F = |
510 new (allocate<MoveRelocatableFixup>()) MoveRelocatableFixup(); | 510 new (allocate<MoveRelocatableFixup>()) MoveRelocatableFixup(); |
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2051 // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and | 2051 // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and |
2052 // iiiiiiii=NumConsecRegs. | 2052 // iiiiiiii=NumConsecRegs. |
2053 constexpr const char *VpushName = "vpush"; | 2053 constexpr const char *VpushName = "vpush"; |
2054 constexpr IValueT VpushOpcode = | 2054 constexpr IValueT VpushOpcode = |
2055 B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9; | 2055 B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9; |
2056 emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs, VpushName); | 2056 emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs, VpushName); |
2057 } | 2057 } |
2058 | 2058 |
2059 } // end of namespace ARM32 | 2059 } // end of namespace ARM32 |
2060 } // end of namespace Ice | 2060 } // end of namespace Ice |
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