Subzero. ARM32. Adds an IsGPR attribute to the register tables.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 164 matching lines @@
     InstructionSet = static_cast<ARM32InstructionSet>(
         (Flags.getTargetInstructionSet() -
          TargetInstructionSet::ARM32InstructionSet_Begin) +
         ARM32InstructionSet::Begin);
   }
 }
 
 namespace {
 constexpr SizeT NumGPRArgs =
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
-          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)              \
+          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(((cc_arg) > 0) ? 1 : 0)
     REGARM32_GPR_TABLE
 #undef X
     ;
 std::array<uint32_t, NumGPRArgs> GPRArgInitializer;
 
 constexpr SizeT NumI64Args =
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
-          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)              \
+          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(((cc_arg) > 0) ? 1 : 0)
     REGARM32_I64PAIR_TABLE
 #undef X
     ;
 std::array<uint32_t, NumI64Args> I64ArgInitializer;
 
 constexpr SizeT NumFP32Args =
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
-          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)              \
+          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(((cc_arg) > 0) ? 1 : 0)
     REGARM32_FP32_TABLE
 #undef X
     ;
 std::array<uint32_t, NumFP32Args> FP32ArgInitializer;
 
 constexpr SizeT NumFP64Args =
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
-          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)              \
+          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(((cc_arg) > 0) ? 1 : 0)
     REGARM32_FP64_TABLE
 #undef X
     ;
 std::array<uint32_t, NumFP64Args> FP64ArgInitializer;
 
 constexpr SizeT NumVec128Args =
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
-          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)              \
+          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(((cc_arg > 0)) ? 1 : 0)
     REGARM32_VEC128_TABLE
 #undef X
     ;
 std::array<uint32_t, NumVec128Args> Vec128ArgInitializer;
 } // end of anonymous namespace
 
 TargetARM32::TargetARM32(Cfg *Func)
     : TargetLowering(Func), NeedSandboxing(Ctx->getFlags().getUseSandboxing()),
       CPUFeatures(Func->getContext()->getFlags()) {}
 
 void TargetARM32::staticInit() {
   // Limit this size (or do all bitsets need to be the same width)???
   llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM);
   ScratchRegs.resize(RegARM32::Reg_NUM);
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
-          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)              \
+          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   IntegerRegisters[RegARM32::val] = isInt;                                     \
   I64PairRegisters[RegARM32::val] = isI64Pair;                                 \
   Float32Registers[RegARM32::val] = isFP32;                                    \
   Float64Registers[RegARM32::val] = isFP64;                                    \
   VectorRegisters[RegARM32::val] = isVec128;                                   \
   RegisterAliases[RegARM32::val].resize(RegARM32::Reg_NUM);                    \
   for (SizeT RegAlias : alias_init) {                                          \
     assert((!RegisterAliases[RegARM32::val][RegAlias] ||                       \
             RegAlias != RegARM32::val) &&                                      \
            "Duplicate alias for " #val);                                       \
@@ skipping 568 matching lines @@
 
 bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) {
   if (auto *Br = llvm::dyn_cast<InstARM32Br>(I)) {
     return Br->optimizeBranch(NextNode);
   }
   return false;
 }
 
 const char *RegARM32::RegNames[] = {
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
-          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)              \
+          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   name,
     REGARM32_TABLE
 #undef X
 };
 
 IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const {
   assert(RegNum < RegARM32::Reg_NUM);
   (void)Ty;
   return RegARM32::RegNames[RegNum];
 }
 
 Variable *TargetARM32::getPhysicalRegister(SizeT RegNum, Type Ty) {
   static const Type DefaultType[] = {
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
-          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)              \
+          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   (isFP32)                                                                     \
       ? IceType_f32                                                            \
       : ((isFP64) ? IceType_f64 : ((isVec128 ? IceType_v4i32 : IceType_i32))),
       REGARM32_TABLE
 #undef X
   };
 
   assert(RegNum < RegARM32::Reg_NUM);
   if (Ty == IceType_void) {
     assert(RegNum < llvm::array_lengthof(DefaultType));
@@ skipping 970 matching lines @@
   }
   llvm::report_fatal_error("Unsupported operand type");
   return nullptr;
 }
 
 llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
                                                  RegSetMask Exclude) const {
   llvm::SmallBitVector Registers(RegARM32::Reg_NUM);
 
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
-          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)              \
+          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   if (scratch && (Include & RegSet_CallerSave))                                \
     Registers[RegARM32::val] = true;                                           \
   if (preserved && (Include & RegSet_CalleeSave))                              \
     Registers[RegARM32::val] = true;                                           \
   if (stackptr && (Include & RegSet_StackPointer))                             \
     Registers[RegARM32::val] = true;                                           \
   if (frameptr && (Include & RegSet_FramePointer))                             \
     Registers[RegARM32::val] = true;                                           \
   if (scratch && (Exclude & RegSet_CallerSave))                                \
     Registers[RegARM32::val] = false;                                          \
@@ skipping 4594 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 llvm::SmallBitVector TargetARM32::ScratchRegs;
 
 } // end of namespace ARM32
 } // end of namespace Ice