Subzero. ARM32. Adds an IsGPR attribute to the register tables.

src/IceInstARM32.def

 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines properties of ARM32 instructions in the form of x-macros.
@@ skipping 17 matching lines @@
 // LR is not considered isInt to avoid being allocated as a register. It is
 // technically preserved, but save/restore is handled separately, based on
 // whether or not the function MaybeLeafFunc.
 //
 // The register tables can be generated using the gen_arm32_reg_tables.py
 // script.
 
 #include "IceRegistersARM32.def"
 // The register tables defined in IceRegistersARM32 use the following x-macro:
 //#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
-//          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
+//          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 
 // We also provide a combined table, so that there is a namespace where all of
 // the registers are considered and have distinct numberings. This is in
 // contrast to the above, where the "encode" is based on how the register
 // numbers will be encoded in binaries and values can overlap.
 #define REGARM32_TABLE                                                         \
   /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,        \
-     isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */                 \
+     isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */          \
   REGARM32_GPR_TABLE                                                           \
   REGARM32_I64PAIR_TABLE                                                       \
   REGARM32_FP32_TABLE                                                          \
   REGARM32_FP64_TABLE                                                          \
   REGARM32_VEC128_TABLE
 //#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
-//          isInt, isFP32, isFP64, isVec128, alias_init)
+//          isGPR, isInt, isFP32, isFP64, isVec128, alias_init)
 
 #define REGARM32_TABLE_BOUNDS                                                  \
   /* val, init */                                                              \
   X(Reg_GPR_First, = Reg_r0)                                                   \
   X(Reg_GPR_Last, = Reg_pc)                                                    \
   X(Reg_I64PAIR_First, = Reg_r0r1)                                             \
   X(Reg_I64PAIR_Last, = Reg_r10fp)                                             \
   X(Reg_SREG_First, = Reg_s0)                                                  \
   X(Reg_SREG_Last, = Reg_s31)                                                  \
   X(Reg_DREG_First, = Reg_d0)                                                  \
@@ skipping 52 matching lines @@
   X(LS, 9, HI, "ls")        /* unsigned lower or same */                       \
   X(GE, 10, LT, "ge")       /* signed greater than or equal */                 \
   X(LT, 11, GE, "lt")       /* signed less than */                             \
   X(GT, 12, LE, "gt")       /* signed greater than */                          \
   X(LE, 13, GT, "le")       /* signed less than or equal */                    \
   X(AL, 14, kNone, "")      /* always (unconditional) */                       \
   X(kNone, 15, kNone, "??") /* special condition / none */
 //#define X(tag, encode, opp, emit)
 
 #endif // SUBZERO_SRC_ICEINSTARM32_DEF