Subzero. ARM32. Adds an IsGPR attribute to the register tables.

pydir/gen_arm32_reg_tables.py

 import os
 import sys
 
 class RegAliases(object):
   def __init__(self, AliasesStr):
     self.Aliases = list(Alias.strip() for Alias in AliasesStr.split(','))
 
   def __str__(self):
     return 'REGLIST{AliasCount}(RegARM32, {Aliases})'.format(
       AliasCount=len(self.Aliases), Aliases=', '.join(self.Aliases))
 
 def _ArgumentNames(Method):
   import inspect
   return (ArgName for ArgName in inspect.getargspec(Method).args
       if ArgName != 'self')
 
 class RegFeatures(object):
   def __init__(self, AsmStr=None, CCArg=0, IsScratch=0, IsPreserved=0,
-               IsStackPtr=0, IsFramePtr=0, IsInt=0, IsI64Pair=0, IsFP32=0,
-               IsFP64=0, IsVec128=0, Aliases=None):
+               IsStackPtr=0, IsFramePtr=0, IsGPR=0, IsInt=0, IsI64Pair=0,
+               IsFP32=0, IsFP64=0, IsVec128=0, Aliases=None):
+    assert (not IsInt) or IsGPR
+    assert (not IsI64Pair) or (not IsGPR)
     assert not (IsInt and IsI64Pair)
     assert not (IsFP32 and IsFP64)
     assert not (IsFP32 and IsVec128)
     assert not (IsFP64 and IsVec128)
-    assert not ((IsInt or IsI64Pair) and (IsFP32 or IsFP64 or IsVec128))
-    assert (not IsFramePtr) or IsInt
-    assert (not IsStackPtr) or not(
-                IsInt or IsI64Pair or IsFP32 or IsFP64 or IsVec128)
+    assert not ((IsGPR) and (IsFP32 or IsFP64 or IsVec128))
+    assert (not IsFramePtr) or IsGPR
+    assert (not IsStackPtr) or IsGPR
     assert not (IsScratch and IsPreserved)
     self.Features = [x for x in _ArgumentNames(self.__init__)]
     self.FeaturesDict = {}
     # The argument Aliases is a string with the register aliasing information.
     # The next line convert it to a RegAlias object, for pretty printing.
     Aliases = RegAliases(Aliases)
     AsmStr = '"%s"' % AsmStr
     for Feature in self.Features:
       self.FeaturesDict[Feature] = locals()[Feature]
 
@@ skipping 25 matching lines @@
     return 'Reg_{Name}, {Encode}, {Features}'.format(Name=self.Name,
       Encode=self.Encode, Features=self.Features)
 
   def IsAnAliasOf(self, Other):
     return Other.Name in self.Features.Aliases().Aliases
 
 # Note: The following tables break the usual 80-col on purpose -- it is easier
 # to read the register tables if each register entry is contained on a single
 # line.
 GPRs = [
-  Reg( 'r0',  0,   IsScratch=1, CCArg=1, IsInt=1,               Aliases= 'r0,  r0r1'),
-  Reg( 'r1',  1,   IsScratch=1, CCArg=2, IsInt=1,               Aliases= 'r1,  r0r1'),
-  Reg( 'r2',  2,   IsScratch=1, CCArg=3, IsInt=1,               Aliases= 'r2,  r2r3'),
-  Reg( 'r3',  3,   IsScratch=1, CCArg=4, IsInt=1,               Aliases= 'r3,  r2r3'),
-  Reg( 'r4',  4, IsPreserved=1,          IsInt=1,               Aliases= 'r4,  r4r5'),
-  Reg( 'r5',  5, IsPreserved=1,          IsInt=1,               Aliases= 'r5,  r4r5'),
-  Reg( 'r6',  6, IsPreserved=1,          IsInt=1,               Aliases= 'r6,  r6r7'),
-  Reg( 'r7',  7, IsPreserved=1,          IsInt=1,               Aliases= 'r7,  r6r7'),
-  Reg( 'r8',  8, IsPreserved=1,          IsInt=1,               Aliases= 'r8,  r8r9'),
-  Reg( 'r9',  9, IsPreserved=1,          IsInt=0,               Aliases= 'r9,  r8r9'),
-  Reg('r10', 10, IsPreserved=1,          IsInt=1,               Aliases='r10, r10fp'),
-  Reg( 'fp', 11, IsPreserved=1,          IsInt=1, IsFramePtr=1, Aliases= 'fp, r10fp'),
-  Reg( 'ip', 12,   IsScratch=1,          IsInt=0,               Aliases= 'ip'),
-  Reg( 'sp', 13,   IsScratch=0,          IsInt=0, IsStackPtr=1, Aliases= 'sp'),
-  Reg( 'lr', 14,   IsScratch=0,          IsInt=0,               Aliases= 'lr'),
-  Reg( 'pc', 15,   IsScratch=0,          IsInt=0,               Aliases= 'pc'),
+  Reg( 'r0',  0,   IsScratch=1, CCArg=1, IsGPR = 1, IsInt=1,               Aliases= 'r0,  r0r1'),
+  Reg( 'r1',  1,   IsScratch=1, CCArg=2, IsGPR = 1, IsInt=1,               Aliases= 'r1,  r0r1'),
+  Reg( 'r2',  2,   IsScratch=1, CCArg=3, IsGPR = 1, IsInt=1,               Aliases= 'r2,  r2r3'),
+  Reg( 'r3',  3,   IsScratch=1, CCArg=4, IsGPR = 1, IsInt=1,               Aliases= 'r3,  r2r3'),
+  Reg( 'r4',  4, IsPreserved=1,          IsGPR = 1, IsInt=1,               Aliases= 'r4,  r4r5'),
+  Reg( 'r5',  5, IsPreserved=1,          IsGPR = 1, IsInt=1,               Aliases= 'r5,  r4r5'),
+  Reg( 'r6',  6, IsPreserved=1,          IsGPR = 1, IsInt=1,               Aliases= 'r6,  r6r7'),
+  Reg( 'r7',  7, IsPreserved=1,          IsGPR = 1, IsInt=1,               Aliases= 'r7,  r6r7'),
+  Reg( 'r8',  8, IsPreserved=1,          IsGPR = 1, IsInt=1,               Aliases= 'r8,  r8r9'),
+  Reg( 'r9',  9, IsPreserved=1,          IsGPR = 1, IsInt=0,               Aliases= 'r9,  r8r9'),
+  Reg('r10', 10, IsPreserved=1,          IsGPR = 1, IsInt=1,               Aliases='r10, r10fp'),
+  Reg( 'fp', 11, IsPreserved=1,          IsGPR = 1, IsInt=1, IsFramePtr=1, Aliases= 'fp, r10fp'),
+  Reg( 'ip', 12,   IsScratch=1,          IsGPR = 1, IsInt=0,               Aliases= 'ip'),
+  Reg( 'sp', 13,   IsScratch=0,          IsGPR = 1, IsInt=0, IsStackPtr=1, Aliases= 'sp'),
+  Reg( 'lr', 14,   IsScratch=0,          IsGPR = 1, IsInt=0,               Aliases= 'lr'),
+  Reg( 'pc', 15,   IsScratch=0,          IsGPR = 1, IsInt=0,               Aliases= 'pc'),
 ]
 
 I64Pairs = [
   Reg( 'r0r1',  0, AsmStr= 'r0, r1',   IsScratch=1, CCArg=1, IsI64Pair=1, Aliases= 'r0r1,  r0, r1'),
   Reg( 'r2r3',  2, AsmStr= 'r2, r3',   IsScratch=1, CCArg=2, IsI64Pair=1, Aliases= 'r2r3,  r2, r3'),
   Reg( 'r4r5',  4, AsmStr= 'r4, r5', IsPreserved=1,          IsI64Pair=1, Aliases= 'r4r5,  r4, r5'),
   Reg( 'r6r7',  6, AsmStr= 'r6, r7', IsPreserved=1,          IsI64Pair=1, Aliases= 'r6r7,  r6, r7'),
   Reg( 'r8r9',  8, AsmStr= 'r8, r9', IsPreserved=1,          IsI64Pair=0, Aliases= 'r8r9,  r8, r9'),
   Reg('r10fp', 10, AsmStr='r10, fp', IsPreserved=1,          IsI64Pair=0, Aliases='r10fp, r10, fp'),
 ]
@@ skipping 113 matching lines @@
        "\n"
        "#ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF\n"
        "#define SUBZERO_SRC_ICEREGISTERSARM32_DEF\n".format(script=os.path.basename(sys.argv[0])))
  
 for Name, RegClass in RegClasses:
   print "#define REGARM32_%s_TABLE" % Name,
   for Reg in RegClass:
     print '\\\n  X({Reg})'.format(Reg=Reg),
   print '\n'
 print "#endif // SUBZERO_SRC_ICEREGISTERSARM32_DEF",