MIPS: [turbofan] Improve matching for And(Shr(x, imm), mask).

src/compiler/mips/instruction-selector-mips.cc

Index: src/compiler/mips/instruction-selector-mips.cc
diff --git a/src/compiler/mips/instruction-selector-mips.cc b/src/compiler/mips/instruction-selector-mips.cc
index 45a1910e7874262708f92059423aaacc1935f998..0ae51f86a5201ccf0617811865c189080a5c9f85 100644
--- a/src/compiler/mips/instruction-selector-mips.cc
+++ b/src/compiler/mips/instruction-selector-mips.cc
@@ -260,17 +260,16 @@ void InstructionSelector::VisitWord32And(Node* node) {
     uint32_t mask = m.right().Value();
     uint32_t mask_width = base::bits::CountPopulation32(mask);
     uint32_t mask_msb = base::bits::CountLeadingZeros32(mask);
-    if ((mask_width != 0) && (mask_msb + mask_width == 32)) {
-      // The mask must be contiguous, and occupy the least-significant bits.
-      DCHECK_EQ(0u, base::bits::CountTrailingZeros32(mask));
-
-      // Select Ext for And(Shr(x, imm), mask) where the mask is in the least
-      // significant bits.
+    uint32_t mask_lsb = base::bits::CountTrailingZeros32(mask);
+    if ((mask_width != 0) && (mask_msb + mask_width + mask_lsb == 32)) {
+      // The mask must be contiguous.
+      // Select Ext for And(Shr(x, imm), mask) where the mask may be in
+      // the least-significant bits or elsewhere.
       Int32BinopMatcher mleft(m.left().node());
       if (mleft.right().HasValue()) {
         // Any shift value can match; int32 shifts use `value % 32`.
         uint32_t lsb = mleft.right().Value() & 0x1f;
-
+        lsb = lsb + mask_lsb;
         // Ext cannot extract bits past the register size, however since
         // shifting the original value would have introduced some zeros we can
         // still use Ext with a smaller mask and the remaining bits will be