MIPS: [turbofan] Improve matching for And(Shr(x, imm), mask).

src/compiler/mips64/instruction-selector-mips64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/adapters.h"
 #include "src/base/bits.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
 
@@ skipping 251 matching lines @@
 
 
 void InstructionSelector::VisitWord32And(Node* node) {
   Mips64OperandGenerator g(this);
   Int32BinopMatcher m(node);
   if (m.left().IsWord32Shr() && CanCover(node, m.left().node()) &&
       m.right().HasValue()) {
     uint32_t mask = m.right().Value();
     uint32_t mask_width = base::bits::CountPopulation32(mask);
     uint32_t mask_msb = base::bits::CountLeadingZeros32(mask);
-    if ((mask_width != 0) && (mask_msb + mask_width == 32)) {
-      // The mask must be contiguous, and occupy the least-significant bits.
-      DCHECK_EQ(0u, base::bits::CountTrailingZeros32(mask));
-
-      // Select Ext for And(Shr(x, imm), mask) where the mask is in the least
-      // significant bits.
+    uint32_t mask_lsb = base::bits::CountTrailingZeros32(mask);
+    if ((mask_width != 0) && (mask_msb + mask_width + mask_lsb == 32)) {
+      // The mask must be contiguous.
+      // Select Ext for And(Shr(x, imm), mask) where the mask may be in
+      // the least-significant bits or elsewhere.
       Int32BinopMatcher mleft(m.left().node());
       if (mleft.right().HasValue()) {
         // Any shift value can match; int32 shifts use `value % 32`.
         uint32_t lsb = mleft.right().Value() & 0x1f;
-
+        lsb = lsb + mask_lsb;
         // Ext cannot extract bits past the register size, however since
         // shifting the original value would have introduced some zeros we can
         // still use Ext with a smaller mask and the remaining bits will be
         // zeros.
         if (lsb + mask_width > 32) mask_width = 32 - lsb;
 
         Emit(kMips64Ext, g.DefineAsRegister(node),
              g.UseRegister(mleft.left().node()), g.TempImmediate(lsb),
              g.TempImmediate(mask_width));
         return;
@@ skipping 19 matching lines @@
 
 
 void InstructionSelector::VisitWord64And(Node* node) {
   Mips64OperandGenerator g(this);
   Int64BinopMatcher m(node);
   if (m.left().IsWord64Shr() && CanCover(node, m.left().node()) &&
       m.right().HasValue()) {
     uint64_t mask = m.right().Value();
     uint32_t mask_width = base::bits::CountPopulation64(mask);
     uint32_t mask_msb = base::bits::CountLeadingZeros64(mask);
-    if ((mask_width != 0) && (mask_msb + mask_width == 64)) {
-      // The mask must be contiguous, and occupy the least-significant bits.
-      DCHECK_EQ(0u, base::bits::CountTrailingZeros64(mask));
-
-      // Select Dext for And(Shr(x, imm), mask) where the mask is in the least
-      // significant bits.
+    uint32_t mask_lsb = base::bits::CountTrailingZeros64(mask);
+    if ((mask_width != 0) && (mask_msb + mask_width + mask_lsb == 64)) {
+      // The mask must be contiguous.
+      // Select Dext for And(Shr(x, imm), mask) where the mask may be in
+      // the least-significant bits or elsewhere.
       Int64BinopMatcher mleft(m.left().node());
       if (mleft.right().HasValue()) {
         // Any shift value can match; int64 shifts use `value % 64`.
         uint32_t lsb = static_cast<uint32_t>(mleft.right().Value() & 0x3f);
-
+        lsb = lsb + mask_lsb;
         // Dext cannot extract bits past the register size, however since
         // shifting the original value would have introduced some zeros we can
         // still use Dext with a smaller mask and the remaining bits will be
         // zeros.
         if (lsb + mask_width > 64) mask_width = 64 - lsb;
-
         Emit(kMips64Dext, g.DefineAsRegister(node),
              g.UseRegister(mleft.left().node()), g.TempImmediate(lsb),
              g.TempImmediate(static_cast<int32_t>(mask_width)));
         return;
       }
       // Other cases fall through to the normal And operation.
     }
   }
   if (m.right().HasValue()) {
     uint64_t mask = m.right().Value();
@@ skipping 1484 matching lines @@
          MachineOperatorBuilder::kFloat32RoundUp |
          MachineOperatorBuilder::kFloat64RoundTruncate |
          MachineOperatorBuilder::kFloat32RoundTruncate |
          MachineOperatorBuilder::kFloat64RoundTiesEven |
          MachineOperatorBuilder::kFloat32RoundTiesEven;
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8