MIPS: [turbofan] Improve matching for And(Shr(x, imm), mask).

MIPS64: [turbofan] Improve matching for And(Shr(x, imm), mask).

Utilise Dextu, Dextm on mips64 for widths and positions larger
than 32.

TEST=
BUG=

Committed: https://crrev.com/8a7f302d806f173171a65e149c11ec86d765d2ef
Cr-Commit-Position: refs/heads/master@{#33138}

[dusan.milosavljevic, 2015-12-27 14:20:37]

dusan.m.milosavljevic@gmail.com changed reviewers:
+ akos.palfi@imgtec.com, balazs.kilvady@imgtec.com, bmeurer@chromium.org,
paul.lind@imgtec.com, titzer@chromium.org

[dusan.milosavljevic, 2015-12-27 14:20:37]

PTAL.

[akos.palfi.imgtec, 2015-12-30 00:32:53]

Please see my inline comment.

Nit in the description: s/utilize Dextm, Dextm/utilize Dextm, Dextu/

https://codereview.chromium.org/1552483002/diff/20001/src/compiler/mips/instr...
File src/compiler/mips/instruction-selector-mips.cc (right):

https://codereview.chromium.org/1552483002/diff/20001/src/compiler/mips/instr...
src/compiler/mips/instruction-selector-mips.cc:281:
g.TempImmediate(mask_width));
When the mask_lsb > 0, the result will be incorrect. The Ext instr will
right-shift the result by 'lsb + mask_lsb', but it must be shifted by 'lsb', so
after the Ext you should shift left the result by 'mask_lsb' to get the correct
result.
Something like this could make it work, but this is a hacky solution and I don't
really like it:

        if (mask_lsb > 0) {
          Emit(kMipsShl, g.DefineAsRegister(node), g.DefineAsRegister(node),
g.TempImmediate(mask_lsb));
        }

Same for mips64.

[dusan.milosavljevic, 2015-12-30 01:50:15]

On 2015/12/30 00:32:53, akos.palfi.imgtec wrote:
> Please see my inline comment.
> 
> Nit in the description: s/utilize Dextm, Dextm/utilize Dextm, Dextu/
> 
>
https://codereview.chromium.org/1552483002/diff/20001/src/compiler/mips/instr...
> File src/compiler/mips/instruction-selector-mips.cc (right):
> 
>
https://codereview.chromium.org/1552483002/diff/20001/src/compiler/mips/instr...
> src/compiler/mips/instruction-selector-mips.cc:281:
> g.TempImmediate(mask_width));
> When the mask_lsb > 0, the result will be incorrect. The Ext instr will
> right-shift the result by 'lsb + mask_lsb', but it must be shifted by 'lsb',
so
> after the Ext you should shift left the result by 'mask_lsb' to get the
correct
> result.
> Something like this could make it work, but this is a hacky solution and I
don't
> really like it:
> 
>         if (mask_lsb > 0) {
>           Emit(kMipsShl, g.DefineAsRegister(node), g.DefineAsRegister(node),
> g.TempImmediate(mask_lsb));
>         }
> 
> Same for mips64.

You are right. I forgot [D]ext is not so powerful, and always right justify
extracted bits. It makes no sense to match it with two instructions.

The mask has to be in lsb,   More cases  matched only for mips64 then using
dext[u, m].

[dusan.milosavljevic, 2015-12-30 02:07:53]

Description was changed from

==========
MIPS: [turbofan] Improve matching for And(Shr(x, imm), mask).

Now mask does not have to be in the least-significant bits only, but
should be contiguous. Shift amount and contiguous mask are independent
for successfull matching.

Additionaly utilize Dextm, Dextm on mips64 for widths and positions larger
than 32.

TEST=
BUG=
==========

to

==========
MIPS64: [turbofan] Improve matching for And(Shr(x, imm), mask).

Utilise Dextu, Dextm on mips64 for widths and positions larger
than 32.

TEST=
BUG=
==========

[akos.palfi.imgtec, 2016-01-05 13:47:54]

LGTM.

[dusan.milosavljevic, 2016-01-06 20:03:32]

The CQ bit was checked by dusan.m.milosavljevic@gmail.com

[commit-bot: I haz the power, 2016-01-06 20:03:45]

CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1552483002/40001
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1552483002/40001

[commit-bot: I haz the power, 2016-01-06 20:24:14]

Description was changed from

==========
MIPS64: [turbofan] Improve matching for And(Shr(x, imm), mask).

Utilise Dextu, Dextm on mips64 for widths and positions larger
than 32.

TEST=
BUG=
==========

to

==========
MIPS64: [turbofan] Improve matching for And(Shr(x, imm), mask).

Utilise Dextu, Dextm on mips64 for widths and positions larger
than 32.

TEST=
BUG=
==========

[commit-bot: I haz the power, 2016-01-06 20:24:15]

Committed patchset #3 (id:40001)

[commit-bot: I haz the power, 2016-01-06 20:24:28]

Description was changed from

==========
MIPS64: [turbofan] Improve matching for And(Shr(x, imm), mask).

Utilise Dextu, Dextm on mips64 for widths and positions larger
than 32.

TEST=
BUG=
==========

to

==========
MIPS64: [turbofan] Improve matching for And(Shr(x, imm), mask).

Utilise Dextu, Dextm on mips64 for widths and positions larger
than 32.

TEST=
BUG=

Committed: https://crrev.com/8a7f302d806f173171a65e149c11ec86d765d2ef
Cr-Commit-Position: refs/heads/master@{#33138}
==========

[commit-bot: I haz the power, 2016-01-06 20:24:31]

Patchset 3 (id:??) landed as
https://crrev.com/8a7f302d806f173171a65e149c11ec86d765d2ef
Cr-Commit-Position: refs/heads/master@{#33138}