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Side by Side Diff: src/IceTargetLoweringMIPS32.h

Issue 1551633002: Subzero. Refactoring. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Addresses comments. Created 4 years, 11 months ago
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1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
11 /// \brief Declares the TargetLoweringMIPS32 class, which implements the 11 /// \brief Declares the TargetLoweringMIPS32 class, which implements the
12 /// TargetLowering interface for the MIPS 32-bit architecture. 12 /// TargetLowering interface for the MIPS 32-bit architecture.
13 /// 13 ///
14 //===----------------------------------------------------------------------===// 14 //===----------------------------------------------------------------------===//
15 15
16 #ifndef SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H 16 #ifndef SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H
17 #define SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H 17 #define SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H
18 18
19 #include "IceAssemblerMIPS32.h"
19 #include "IceDefs.h" 20 #include "IceDefs.h"
20 #include "IceInstMIPS32.h" 21 #include "IceInstMIPS32.h"
21 #include "IceRegistersMIPS32.h" 22 #include "IceRegistersMIPS32.h"
22 #include "IceTargetLowering.h" 23 #include "IceTargetLowering.h"
23 24
24 namespace Ice { 25 namespace Ice {
25 26
26 class TargetMIPS32 : public TargetLowering { 27 class TargetMIPS32 : public TargetLowering {
27 TargetMIPS32() = delete; 28 TargetMIPS32() = delete;
28 TargetMIPS32(const TargetMIPS32 &) = delete; 29 TargetMIPS32(const TargetMIPS32 &) = delete;
29 TargetMIPS32 &operator=(const TargetMIPS32 &) = delete; 30 TargetMIPS32 &operator=(const TargetMIPS32 &) = delete;
30 31
31 public: 32 public:
33 ~TargetMIPS32() override = default;
34
32 static void staticInit(); 35 static void staticInit();
33 // TODO(jvoung): return a unique_ptr. 36 static std::unique_ptr<::Ice::TargetLowering> create(Cfg *Func) {
34 static TargetMIPS32 *create(Cfg *Func) { return new TargetMIPS32(Func); } 37 return makeUnique<TargetMIPS32>(Func);
38 }
39
40 std::unique_ptr<::Ice::Assembler> createAssembler() const override {
41 return makeUnique<MIPS32::AssemblerMIPS32>();
42 }
35 43
36 void translateOm1() override; 44 void translateOm1() override;
37 void translateO2() override; 45 void translateO2() override;
38 bool doBranchOpt(Inst *I, const CfgNode *NextNode) override; 46 bool doBranchOpt(Inst *I, const CfgNode *NextNode) override;
39 47
40 SizeT getNumRegisters() const override { return RegMIPS32::Reg_NUM; } 48 SizeT getNumRegisters() const override { return RegMIPS32::Reg_NUM; }
41 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override; 49 Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override;
42 IceString getRegName(SizeT RegNum, Type Ty) const override; 50 IceString getRegName(SizeT RegNum, Type Ty) const override;
43 llvm::SmallBitVector getRegisterSet(RegSetMask Include, 51 llvm::SmallBitVector getRegisterSet(RegSetMask Include,
44 RegSetMask Exclude) const override; 52 RegSetMask Exclude) const override;
(...skipping 205 matching lines...) Expand 10 before | Expand all | Expand 10 after
250 258
251 bool UsesFramePointer = false; 259 bool UsesFramePointer = false;
252 bool NeedsStackAlignment = false; 260 bool NeedsStackAlignment = false;
253 static llvm::SmallBitVector TypeToRegisterSet[RCMIPS32_NUM]; 261 static llvm::SmallBitVector TypeToRegisterSet[RCMIPS32_NUM];
254 static llvm::SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM]; 262 static llvm::SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM];
255 static llvm::SmallBitVector ScratchRegs; 263 static llvm::SmallBitVector ScratchRegs;
256 llvm::SmallBitVector RegsUsed; 264 llvm::SmallBitVector RegsUsed;
257 VarList PhysicalRegisters[IceType_NUM]; 265 VarList PhysicalRegisters[IceType_NUM];
258 266
259 private: 267 private:
260 ~TargetMIPS32() override = default; 268 ENABLE_MAKE_UNIQUE;
261 }; 269 };
262 270
263 class TargetDataMIPS32 final : public TargetDataLowering { 271 class TargetDataMIPS32 final : public TargetDataLowering {
264 TargetDataMIPS32() = delete; 272 TargetDataMIPS32() = delete;
265 TargetDataMIPS32(const TargetDataMIPS32 &) = delete; 273 TargetDataMIPS32(const TargetDataMIPS32 &) = delete;
266 TargetDataMIPS32 &operator=(const TargetDataMIPS32 &) = delete; 274 TargetDataMIPS32 &operator=(const TargetDataMIPS32 &) = delete;
267 275
268 public: 276 public:
269 static std::unique_ptr<TargetDataLowering> create(GlobalContext *Ctx) { 277 static std::unique_ptr<TargetDataLowering> create(GlobalContext *Ctx) {
270 return std::unique_ptr<TargetDataLowering>(new TargetDataMIPS32(Ctx)); 278 return std::unique_ptr<TargetDataLowering>(new TargetDataMIPS32(Ctx));
(...skipping 27 matching lines...) Expand all
298 protected: 306 protected:
299 explicit TargetHeaderMIPS32(GlobalContext *Ctx); 307 explicit TargetHeaderMIPS32(GlobalContext *Ctx);
300 308
301 private: 309 private:
302 ~TargetHeaderMIPS32() = default; 310 ~TargetHeaderMIPS32() = default;
303 }; 311 };
304 312
305 } // end of namespace Ice 313 } // end of namespace Ice
306 314
307 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H 315 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H
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