Subzero. Refactoring.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Declares the TargetLoweringARM32 class, which implements the
 /// TargetLowering interface for the ARM 32-bit architecture.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICETARGETLOWERINGARM32_H
 #define SUBZERO_SRC_ICETARGETLOWERINGARM32_H
 
+#include "IceAssemblerARM32.h"
 #include "IceDefs.h"
 #include "IceInstARM32.h"
 #include "IceRegistersARM32.h"
 #include "IceTargetLowering.h"
 
 #include "llvm/ADT/SmallBitVector.h"
 
 namespace Ice {
 
 // Class encapsulating ARM cpu features / instruction set.
@@ skipping 19 matching lines @@
   ARM32InstructionSet InstructionSet = ARM32InstructionSet::Begin;
 };
 
 // The target lowering logic for ARM32.
 class TargetARM32 : public TargetLowering {
   TargetARM32() = delete;
   TargetARM32(const TargetARM32 &) = delete;
   TargetARM32 &operator=(const TargetARM32 &) = delete;
 
 public:
+  ~TargetARM32() = default;
+
   static void staticInit();
   // TODO(jvoung): return a unique_ptr.
-  static TargetARM32 *create(Cfg *Func) { return new TargetARM32(Func); }
+  static std::unique_ptr<::Ice::TargetLowering> create(Cfg *Func) {
+    return makeUnique<TargetARM32>(Func);
+  }
+
+  std::unique_ptr<::Ice::Assembler> createAssembler() const override {
+    return makeUnique<ARM32::AssemblerARM32>();
+  }
 
   void initNodeForLowering(CfgNode *Node) override {
     Computations.forgetProducers();
     Computations.recordProducers(Node);
     Computations.dump(Func);
   }
 
   void translateOm1() override;
   void translateO2() override;
   bool doBranchOpt(Inst *I, const CfgNode *NextNode) override;
@@ skipping 979 matching lines @@
     CfgVector<SizeT> I64Args;
 
     void discardUnavailableVFPRegs(CfgVector<SizeT> *Regs);
     llvm::SmallBitVector VFPRegsUsed;
     CfgVector<SizeT> FP32Args;
     CfgVector<SizeT> FP64Args;
     CfgVector<SizeT> Vec128Args;
   };
 
 private:
-  ~TargetARM32() override = default;
+  ENABLE_MAKE_UNIQUE;
 
   OperandARM32Mem *formAddressingMode(Type Ty, Cfg *Func, const Inst *LdSt,
                                       Operand *Base);
 
   void postambleCtpop64(const InstCall *Instr);
   void preambleDivRem(const InstCall *Instr);
   std::unordered_map<Operand *, void (TargetARM32::*)(const InstCall *Inst)>
       ARM32HelpersPreamble;
   std::unordered_map<Operand *, void (TargetARM32::*)(const InstCall *Inst)>
       ARM32HelpersPostamble;
@@ skipping 122 matching lines @@
 
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H