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1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// | 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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28 #include "IcePhiLoweringImpl.h" | 28 #include "IcePhiLoweringImpl.h" |
29 #include "IceRegistersARM32.h" | 29 #include "IceRegistersARM32.h" |
30 #include "IceTargetLoweringARM32.def" | 30 #include "IceTargetLoweringARM32.def" |
31 #include "IceUtils.h" | 31 #include "IceUtils.h" |
32 #include "llvm/Support/MathExtras.h" | 32 #include "llvm/Support/MathExtras.h" |
33 | 33 |
34 #include <algorithm> | 34 #include <algorithm> |
35 #include <array> | 35 #include <array> |
36 #include <utility> | 36 #include <utility> |
37 | 37 |
| 38 namespace ARM32 { |
| 39 std::unique_ptr<::Ice::TargetLowering> createTargetLowering(::Ice::Cfg *Func) { |
| 40 return ::Ice::TargetARM32::create(Func); |
| 41 } |
| 42 |
| 43 std::unique_ptr<::Ice::TargetDataLowering> |
| 44 createTargetDataLowering(::Ice::GlobalContext *Ctx) { |
| 45 return ::Ice::TargetDataARM32::create(Ctx); |
| 46 } |
| 47 |
| 48 std::unique_ptr<::Ice::TargetHeaderLowering> |
| 49 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) { |
| 50 return ::Ice::TargetHeaderARM32::create(Ctx); |
| 51 } |
| 52 |
| 53 void staticInit() { ::Ice::TargetARM32::staticInit(); } |
| 54 } // end of namespace ARM32 |
| 55 |
38 namespace Ice { | 56 namespace Ice { |
39 | 57 |
40 namespace { | 58 namespace { |
41 | 59 |
42 // The following table summarizes the logic for lowering the icmp instruction | 60 // The following table summarizes the logic for lowering the icmp instruction |
43 // for i32 and narrower types. Each icmp condition has a clear mapping to an | 61 // for i32 and narrower types. Each icmp condition has a clear mapping to an |
44 // ARM32 conditional move instruction. | 62 // ARM32 conditional move instruction. |
45 | 63 |
46 const struct TableIcmp32_ { | 64 const struct TableIcmp32_ { |
47 CondARM32::Cond Mapping; | 65 CondARM32::Cond Mapping; |
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6423 // Technically R9 is used for TLS with Sandboxing, and we reserve it. | 6441 // Technically R9 is used for TLS with Sandboxing, and we reserve it. |
6424 // However, for compatibility with current NaCl LLVM, don't claim that. | 6442 // However, for compatibility with current NaCl LLVM, don't claim that. |
6425 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; | 6443 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; |
6426 } | 6444 } |
6427 | 6445 |
6428 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM]; | 6446 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM]; |
6429 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; | 6447 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; |
6430 llvm::SmallBitVector TargetARM32::ScratchRegs; | 6448 llvm::SmallBitVector TargetARM32::ScratchRegs; |
6431 | 6449 |
6432 } // end of namespace Ice | 6450 } // end of namespace Ice |
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