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1 /* Copyright (c) 2007, Google Inc. | |
2 * All rights reserved. | |
3 * | |
4 * Redistribution and use in source and binary forms, with or without | |
5 * modification, are permitted provided that the following conditions are | |
6 * met: | |
7 * | |
8 * * Redistributions of source code must retain the above copyright | |
9 * notice, this list of conditions and the following disclaimer. | |
10 * * Redistributions in binary form must reproduce the above | |
11 * copyright notice, this list of conditions and the following disclaimer | |
12 * in the documentation and/or other materials provided with the | |
13 * distribution. | |
14 * * Neither the name of Google Inc. nor the names of its | |
15 * contributors may be used to endorse or promote products derived from | |
16 * this software without specific prior written permission. | |
17 * | |
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
29 * | |
30 * --- | |
31 * This module gets enough CPU information to optimize the | |
32 * atomicops module on x86. | |
33 */ | |
34 | |
35 #include "base/atomicops.h" | |
36 #include "base/basictypes.h" | |
37 #include "base/googleinit.h" | |
38 #include "base/logging.h" | |
39 #include <string.h> | |
40 | |
41 // This file only makes sense with atomicops-internals-x86.h -- it | |
42 // depends on structs that are defined in that file. If atomicops.h | |
43 // doesn't sub-include that file, then we aren't needed, and shouldn't | |
44 // try to do anything. | |
45 #ifdef BASE_ATOMICOPS_INTERNALS_X86_H_ | |
46 | |
47 // Inline cpuid instruction. In PIC compilations, %ebx contains the address | |
48 // of the global offset table. To avoid breaking such executables, this code | |
49 // must preserve that register's value across cpuid instructions. | |
50 #if defined(__i386__) | |
51 #define cpuid(a, b, c, d, inp) \ | |
52 asm ("mov %%ebx, %%edi\n" \ | |
53 "cpuid\n" \ | |
54 "xchg %%edi, %%ebx\n" \ | |
55 : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) | |
56 #elif defined (__x86_64__) | |
57 #define cpuid(a, b, c, d, inp) \ | |
58 asm ("mov %%rbx, %%rdi\n" \ | |
59 "cpuid\n" \ | |
60 "xchg %%rdi, %%rbx\n" \ | |
61 : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) | |
62 #endif | |
63 | |
64 #if defined(cpuid) // initialize the struct only on x86 | |
65 | |
66 // Set the flags so that code will run correctly and conservatively | |
67 // until InitGoogle() is called. | |
68 struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = { | |
69 false, // bug can't exist before process spawns multiple threads | |
70 false, // no SSE2 | |
71 false, // no cmpxchg16b | |
72 }; | |
73 | |
74 // Initialize the AtomicOps_Internalx86CPUFeatures struct. | |
75 static void AtomicOps_Internalx86CPUFeaturesInit() { | |
76 uint32 eax; | |
77 uint32 ebx; | |
78 uint32 ecx; | |
79 uint32 edx; | |
80 | |
81 // Get vendor string (issue CPUID with eax = 0) | |
82 cpuid(eax, ebx, ecx, edx, 0); | |
83 char vendor[13]; | |
84 memcpy(vendor, &ebx, 4); | |
85 memcpy(vendor + 4, &edx, 4); | |
86 memcpy(vendor + 8, &ecx, 4); | |
87 vendor[12] = 0; | |
88 | |
89 // get feature flags in ecx/edx, and family/model in eax | |
90 cpuid(eax, ebx, ecx, edx, 1); | |
91 | |
92 int family = (eax >> 8) & 0xf; // family and model fields | |
93 int model = (eax >> 4) & 0xf; | |
94 if (family == 0xf) { // use extended family and model fields | |
95 family += (eax >> 20) & 0xff; | |
96 model += ((eax >> 16) & 0xf) << 4; | |
97 } | |
98 | |
99 // Opteron Rev E has a bug in which on very rare occasions a locked | |
100 // instruction doesn't act as a read-acquire barrier if followed by a | |
101 // non-locked read-modify-write instruction. Rev F has this bug in | |
102 // pre-release versions, but not in versions released to customers, | |
103 // so we test only for Rev E, which is family 15, model 32..63 inclusive. | |
104 if (strcmp(vendor, "AuthenticAMD") == 0 && // AMD | |
105 family == 15 && | |
106 32 <= model && model <= 63) { | |
107 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true; | |
108 } else { | |
109 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false; | |
110 } | |
111 | |
112 // edx bit 26 is SSE2 which we use to tell use whether we can use mfence | |
113 AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1); | |
114 | |
115 // ecx bit 13 indicates whether the cmpxchg16b instruction is supported | |
116 AtomicOps_Internalx86CPUFeatures.has_cmpxchg16b = ((ecx >> 13) & 1); | |
117 } | |
118 | |
119 REGISTER_MODULE_INITIALIZER(atomicops_x86, { | |
120 AtomicOps_Internalx86CPUFeaturesInit(); | |
121 }); | |
122 | |
123 #endif | |
124 | |
125 #endif /* ifdef BASE_ATOMICOPS_INTERNALS_X86_H_ */ | |
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