Subzero. Code organization.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringX86Base class, which consists almost
 /// entirely of the lowering sequence for each high-level instruction.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H
 #define SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H
 
 #include "IceCfg.h"
 #include "IceCfgNode.h"
 #include "IceClFlags.h"
 #include "IceDefs.h"
 #include "IceELFObjectWriter.h"
 #include "IceGlobalInits.h"
 #include "IceInstVarIter.h"
 #include "IceLiveness.h"
 #include "IceOperand.h"
 #include "IcePhiLoweringImpl.h"
 #include "IceUtils.h"
+#include "IceInstX86Base.h"

[Jim Stichnoth, 2016/01/03 18:20:02]

alphabetize includes

 #include "llvm/Support/MathExtras.h"
 
 #include <stack>
 
 namespace Ice {
-namespace X86Internal {
+namespace X86NAMESPACE {
 
 /// A helper class to ease the settings of RandomizationPoolingPause to disable
 /// constant blinding or pooling for some translation phases.
 class BoolFlagSaver {
   BoolFlagSaver() = delete;
   BoolFlagSaver(const BoolFlagSaver &) = delete;
   BoolFlagSaver &operator=(const BoolFlagSaver &) = delete;
 
 public:
   BoolFlagSaver(bool &F, bool NewValue) : OldValue(F), Flag(F) { F = NewValue; }
   ~BoolFlagSaver() { Flag = OldValue; }
 
 private:
   const bool OldValue;
   bool &Flag;
 };
 
-template <class MachineTraits> class BoolFoldingEntry {
+template <typename Traits> class BoolFoldingEntry {
   BoolFoldingEntry(const BoolFoldingEntry &) = delete;
 
 public:
   BoolFoldingEntry() = default;
   explicit BoolFoldingEntry(Inst *I);
   BoolFoldingEntry &operator=(const BoolFoldingEntry &) = default;
   /// Instr is the instruction producing the i1-type variable of interest.
   Inst *Instr = nullptr;
   /// IsComplex is the cached result of BoolFolding::hasComplexLowering(Instr).
   bool IsComplex = false;
   /// IsLiveOut is initialized conservatively to true, and is set to false when
   /// we encounter an instruction that ends Var's live range. We disable the
   /// folding optimization when Var is live beyond this basic block. Note that
   /// if liveness analysis is not performed (e.g. in Om1 mode), IsLiveOut will
   /// always be true and the folding optimization will never be performed.
   bool IsLiveOut = true;
   // NumUses counts the number of times Var is used as a source operand in the
   // basic block. If IsComplex is true and there is more than one use of Var,
   // then the folding optimization is disabled for Var.
   uint32_t NumUses = 0;
 };
 
-template <class MachineTraits> class BoolFolding {
+template <typename Traits> class BoolFolding {
 public:
   enum BoolFoldingProducerKind {
     PK_None,
     // TODO(jpp): PK_Icmp32 is no longer meaningful. Rename to PK_IcmpNative.
     PK_Icmp32,
     PK_Icmp64,
     PK_Fcmp,
     PK_Trunc,
     PK_Arith // A flag-setting arithmetic instruction.
   };
@@ skipping 19 matching lines @@
   void dump(const Cfg *Func) const;
 
 private:
   /// Returns true if Producers contains a valid entry for the given VarNum.
   bool containsValid(SizeT VarNum) const {
     auto Element = Producers.find(VarNum);
     return Element != Producers.end() && Element->second.Instr != nullptr;
   }
   void setInvalid(SizeT VarNum) { Producers[VarNum].Instr = nullptr; }
   /// Producers maps Variable::Number to a BoolFoldingEntry.
-  std::unordered_map<SizeT, BoolFoldingEntry<MachineTraits>> Producers;
+  std::unordered_map<SizeT, BoolFoldingEntry<Traits>> Producers;
 };
 
-template <class MachineTraits>
-BoolFoldingEntry<MachineTraits>::BoolFoldingEntry(Inst *I)
-    : Instr(I), IsComplex(BoolFolding<MachineTraits>::hasComplexLowering(I)) {}
+template <typename Traits>
+BoolFoldingEntry<Traits>::BoolFoldingEntry(Inst *I)
+    : Instr(I), IsComplex(BoolFolding<Traits>::hasComplexLowering(I)) {}
 
-template <class MachineTraits>
-typename BoolFolding<MachineTraits>::BoolFoldingProducerKind
-BoolFolding<MachineTraits>::getProducerKind(const Inst *Instr) {
+template <typename Traits>
+typename BoolFolding<Traits>::BoolFoldingProducerKind
+BoolFolding<Traits>::getProducerKind(const Inst *Instr) {
   if (llvm::isa<InstIcmp>(Instr)) {
-    if (MachineTraits::Is64Bit || Instr->getSrc(0)->getType() != IceType_i64)
+    if (Traits::Is64Bit || Instr->getSrc(0)->getType() != IceType_i64)
       return PK_Icmp32;
     return PK_Icmp64;
   }
   if (llvm::isa<InstFcmp>(Instr))
     return PK_Fcmp;
   if (auto *Arith = llvm::dyn_cast<InstArithmetic>(Instr)) {
-    if (MachineTraits::Is64Bit || Arith->getSrc(0)->getType() != IceType_i64) {
+    if (Traits::Is64Bit || Arith->getSrc(0)->getType() != IceType_i64) {
       switch (Arith->getOp()) {
       default:
         return PK_None;
       case InstArithmetic::And:
       case InstArithmetic::Or:
         return PK_Arith;
       }
     }
   }
   return PK_None; // TODO(stichnot): remove this
 
   if (auto *Cast = llvm::dyn_cast<InstCast>(Instr)) {
     switch (Cast->getCastKind()) {
     default:
       return PK_None;
     case InstCast::Trunc:
       return PK_Trunc;
     }
   }
   return PK_None;
 }
 
-template <class MachineTraits>
-typename BoolFolding<MachineTraits>::BoolFoldingConsumerKind
-BoolFolding<MachineTraits>::getConsumerKind(const Inst *Instr) {
+template <typename Traits>
+typename BoolFolding<Traits>::BoolFoldingConsumerKind
+BoolFolding<Traits>::getConsumerKind(const Inst *Instr) {
   if (llvm::isa<InstBr>(Instr))
     return CK_Br;
   if (llvm::isa<InstSelect>(Instr))
     return CK_Select;
   return CK_None; // TODO(stichnot): remove this
 
   if (auto *Cast = llvm::dyn_cast<InstCast>(Instr)) {
     switch (Cast->getCastKind()) {
     default:
       return CK_None;
     case InstCast::Sext:
       return CK_Sext;
     case InstCast::Zext:
       return CK_Zext;
     }
   }
   return CK_None;
 }
 
 /// Returns true if the producing instruction has a "complex" lowering sequence.
 /// This generally means that its lowering sequence requires more than one
 /// conditional branch, namely 64-bit integer compares and some floating-point
 /// compares. When this is true, and there is more than one consumer, we prefer
 /// to disable the folding optimization because it minimizes branches.
-template <class MachineTraits>
-bool BoolFolding<MachineTraits>::hasComplexLowering(const Inst *Instr) {
+template <typename Traits>
+bool BoolFolding<Traits>::hasComplexLowering(const Inst *Instr) {
   switch (getProducerKind(Instr)) {
   default:
     return false;
   case PK_Icmp64:
-    return !MachineTraits::Is64Bit;
+    return !Traits::Is64Bit;
   case PK_Fcmp:
-    return MachineTraits::TableFcmp[llvm::cast<InstFcmp>(Instr)->getCondition()]
-               .C2 != MachineTraits::Cond::Br_None;
+    return Traits::TableFcmp[llvm::cast<InstFcmp>(Instr)->getCondition()].C2 !=
+           Traits::Cond::Br_None;
   }
 }
 
-template <class MachineTraits>
-bool BoolFolding<MachineTraits>::isValidFolding(
-    typename BoolFolding<MachineTraits>::BoolFoldingProducerKind ProducerKind,
-    typename BoolFolding<MachineTraits>::BoolFoldingConsumerKind ConsumerKind) {
+template <typename Traits>
+bool BoolFolding<Traits>::isValidFolding(
+    typename BoolFolding<Traits>::BoolFoldingProducerKind ProducerKind,
+    typename BoolFolding<Traits>::BoolFoldingConsumerKind ConsumerKind) {
   switch (ProducerKind) {
   default:
     return false;
   case PK_Icmp32:
   case PK_Icmp64:
   case PK_Fcmp:
     return (ConsumerKind == CK_Br) || (ConsumerKind == CK_Select);
   case PK_Arith:
     return ConsumerKind == CK_Br;
   }
 }
 
-template <class MachineTraits>
-void BoolFolding<MachineTraits>::init(CfgNode *Node) {
+template <typename Traits> void BoolFolding<Traits>::init(CfgNode *Node) {
   Producers.clear();
   for (Inst &Instr : Node->getInsts()) {
     // Check whether Instr is a valid producer.
     Variable *Var = Instr.getDest();
     if (!Instr.isDeleted() // only consider non-deleted instructions
         && Var             // only instructions with an actual dest var
         && Var->getType() == IceType_i1          // only bool-type dest vars
         && getProducerKind(&Instr) != PK_None) { // white-listed instructions
-      Producers[Var->getIndex()] = BoolFoldingEntry<MachineTraits>(&Instr);
+      Producers[Var->getIndex()] = BoolFoldingEntry<Traits>(&Instr);
     }
     // Check each src variable against the map.
     FOREACH_VAR_IN_INST(Var, Instr) {
       SizeT VarNum = Var->getIndex();
       if (!containsValid(VarNum))
         continue;
       // All valid consumers use Var as the first source operand
       if (IndexOfVarOperandInInst(Var) != 0) {
         setInvalid(VarNum);
         continue;
       }
       // Consumer instructions must be white-listed
-      typename BoolFolding<MachineTraits>::BoolFoldingConsumerKind
-          ConsumerKind = getConsumerKind(&Instr);
+      typename BoolFolding<Traits>::BoolFoldingConsumerKind ConsumerKind =
+          getConsumerKind(&Instr);
       if (ConsumerKind == CK_None) {
         setInvalid(VarNum);
         continue;
       }
-      typename BoolFolding<MachineTraits>::BoolFoldingProducerKind
-          ProducerKind = getProducerKind(Producers[VarNum].Instr);
+      typename BoolFolding<Traits>::BoolFoldingProducerKind ProducerKind =
+          getProducerKind(Producers[VarNum].Instr);
       if (!isValidFolding(ProducerKind, ConsumerKind)) {
         setInvalid(VarNum);
         continue;
       }
       // Avoid creating multiple copies of complex producer instructions.
       if (Producers[VarNum].IsComplex && Producers[VarNum].NumUses > 0) {
         setInvalid(VarNum);
         continue;
       }
       ++Producers[VarNum].NumUses;
@@ skipping 12 matching lines @@
       continue;
     }
     // Mark as "dead" rather than outright deleting. This is so that other
     // peephole style optimizations during or before lowering have access to
     // this instruction in undeleted form. See for example
     // tryOptimizedCmpxchgCmpBr().
     I.second.Instr->setDead();
   }
 }
 
-template <class MachineTraits>
-const Inst *
-BoolFolding<MachineTraits>::getProducerFor(const Operand *Opnd) const {
+template <typename Traits>
+const Inst *BoolFolding<Traits>::getProducerFor(const Operand *Opnd) const {
   auto *Var = llvm::dyn_cast<const Variable>(Opnd);
   if (Var == nullptr)
     return nullptr;
   SizeT VarNum = Var->getIndex();
   auto Element = Producers.find(VarNum);
   if (Element == Producers.end())
     return nullptr;
   return Element->second.Instr;
 }
 
-template <class MachineTraits>
-void BoolFolding<MachineTraits>::dump(const Cfg *Func) const {
+template <typename Traits>
+void BoolFolding<Traits>::dump(const Cfg *Func) const {
   if (!BuildDefs::dump() || !Func->isVerbose(IceV_Folding))
     return;
   OstreamLocker L(Func->getContext());
   Ostream &Str = Func->getContext()->getStrDump();
   for (auto &I : Producers) {
     if (I.second.Instr == nullptr)
       continue;
     Str << "Found foldable producer:\n  ";
     I.second.Instr->dump(Func);
     Str << "\n";
   }
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::initNodeForLowering(CfgNode *Node) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::initNodeForLowering(CfgNode *Node) {
   FoldingInfo.init(Node);
   FoldingInfo.dump(Func);
 }
 
-template <class Machine>
-TargetX86Base<Machine>::TargetX86Base(Cfg *Func)
+template <typename TraitsType>
+TargetX86Base<TraitsType>::TargetX86Base(Cfg *Func)
     : TargetLowering(Func) {
   static_assert(
       (Traits::InstructionSet::End - Traits::InstructionSet::Begin) ==
           (TargetInstructionSet::X86InstructionSet_End -
            TargetInstructionSet::X86InstructionSet_Begin),
       "Traits::InstructionSet range different from TargetInstructionSet");
   if (Func->getContext()->getFlags().getTargetInstructionSet() !=
       TargetInstructionSet::BaseInstructionSet) {
-    InstructionSet = static_cast<typename Traits::InstructionSet>(
+    InstructionSet = static_cast<InstructionSetEnum>(
         (Func->getContext()->getFlags().getTargetInstructionSet() -
          TargetInstructionSet::X86InstructionSet_Begin) +
         Traits::InstructionSet::Begin);
   }
 }
 
-template <class Machine> void TargetX86Base<Machine>::staticInit() {
+template <typename TraitsType> void TargetX86Base<TraitsType>::staticInit() {
   Traits::initRegisterSet(&TypeToRegisterSet, &RegisterAliases, &ScratchRegs);
 }
 
-template <class Machine> void TargetX86Base<Machine>::translateO2() {
+template <typename TraitsType> void TargetX86Base<TraitsType>::translateO2() {
   TimerMarker T(TimerStack::TT_O2, Func);
 
   genTargetHelperCalls();
   Func->dump("After target helper call insertion");
 
   // Merge Alloca instructions, and lay out the stack.
   static constexpr bool SortAndCombineAllocas = true;
   Func->processAllocas(SortAndCombineAllocas);
   Func->dump("After Alloca processing");
 
@@ skipping 105 matching lines @@
   Func->dump("After branch optimization");
 
   // Nop insertion if -nop-insertion is enabled.
   Func->doNopInsertion();
 
   // Mark nodes that require sandbox alignment
   if (Ctx->getFlags().getUseSandboxing())
     Func->markNodesForSandboxing();
 }
 
-template <class Machine> void TargetX86Base<Machine>::translateOm1() {
+template <typename TraitsType> void TargetX86Base<TraitsType>::translateOm1() {
   TimerMarker T(TimerStack::TT_Om1, Func);
 
   genTargetHelperCalls();
 
   // Do not merge Alloca instructions, and lay out the stack.
   static constexpr bool SortAndCombineAllocas = false;
   Func->processAllocas(SortAndCombineAllocas);
   Func->dump("After Alloca processing");
 
   Func->placePhiLoads();
@@ skipping 56 matching lines @@
   case InstArithmetic::Xor:
     return true;
   case InstArithmetic::Shl:
   case InstArithmetic::Lshr:
   case InstArithmetic::Ashr:
     return false; // TODO(stichnot): implement
     return !isI64;
   }
 }
 
-template <class Machine>
+template <typename TraitsType>
 bool isSameMemAddressOperand(const Operand *A, const Operand *B) {
   if (A == B)
     return true;
-  if (auto *MemA = llvm::dyn_cast<
-          typename TargetX86Base<Machine>::Traits::X86OperandMem>(A)) {
-    if (auto *MemB = llvm::dyn_cast<
-            typename TargetX86Base<Machine>::Traits::X86OperandMem>(B)) {
+  if (auto *MemA =
+          llvm::dyn_cast<typename TargetX86Base<TraitsType>::X86OperandMem>(
+              A)) {
+    if (auto *MemB =
+            llvm::dyn_cast<typename TargetX86Base<TraitsType>::X86OperandMem>(
+                B)) {
       return MemA->getBase() == MemB->getBase() &&
              MemA->getOffset() == MemB->getOffset() &&
              MemA->getIndex() == MemB->getIndex() &&
              MemA->getShift() == MemB->getShift() &&
              MemA->getSegmentRegister() == MemB->getSegmentRegister();
     }
   }
   return false;
 }
 
-template <class Machine> void TargetX86Base<Machine>::findRMW() {
+template <typename TraitsType> void TargetX86Base<TraitsType>::findRMW() {
   Func->dump("Before RMW");
   if (Func->isVerbose(IceV_RMW))
     Func->getContext()->lockStr();
   for (CfgNode *Node : Func->getNodes()) {
     // Walk through the instructions, considering each sequence of 3
     // instructions, and look for the particular RMW pattern. Note that this
     // search can be "broken" (false negatives) if there are intervening
     // deleted instructions, or intervening instructions that could be safely
     // moved out of the way to reveal an RMW pattern.
     auto E = Node->getInsts().end();
@@ skipping 33 matching lines @@
       // x's live range, and therefore the RMW instruction will be retained and
       // later lowered.  On the other hand, if the RMW instruction does not end
       // x's live range, then the Store instruction must still be present, and
       // therefore the RMW instruction is ignored during lowering because it is
       // redundant with the Store instruction.
       //
       // Note that if "a" has further uses, the RMW transformation may still
       // trigger, resulting in two loads and one store, which is worse than the
       // original one load and one store.  However, this is probably rare, and
       // caching probably keeps it just as fast.
-      if (!isSameMemAddressOperand<Machine>(Load->getSourceAddress(),
-                                            Store->getAddr()))
+      if (!isSameMemAddressOperand<TraitsType>(Load->getSourceAddress(),
+                                               Store->getAddr()))
         continue;
       Operand *ArithSrcFromLoad = Arith->getSrc(0);
       Operand *ArithSrcOther = Arith->getSrc(1);
       if (ArithSrcFromLoad != Load->getDest()) {
         if (!Arith->isCommutative() || ArithSrcOther != Load->getDest())
           continue;
         std::swap(ArithSrcFromLoad, ArithSrcOther);
       }
       if (Arith->getDest() != Store->getData())
         continue;
       if (!canRMW(Arith))
         continue;
       if (Func->isVerbose(IceV_RMW)) {
         Ostream &Str = Func->getContext()->getStrDump();
         Str << "Found RMW in " << Func->getFunctionName() << ":\n  ";
         Load->dump(Func);
         Str << "\n  ";
         Arith->dump(Func);
         Str << "\n  ";
         Store->dump(Func);
         Str << "\n";
       }
       Variable *Beacon = Func->makeVariable(IceType_i32);
       Beacon->setMustNotHaveReg();
       Store->setRmwBeacon(Beacon);
       auto *BeaconDef = InstFakeDef::create(Func, Beacon);
       Node->getInsts().insert(I3, BeaconDef);
-      auto *RMW = Traits::Insts::FakeRMW::create(
-          Func, ArithSrcOther, Store->getAddr(), Beacon, Arith->getOp());
+      auto *RMW = InstX86FakeRMW::create(Func, ArithSrcOther, Store->getAddr(),
+                                         Beacon, Arith->getOp());
       Node->getInsts().insert(I3, RMW);
     }
   }
   if (Func->isVerbose(IceV_RMW))
     Func->getContext()->unlockStr();
 }
 
 // Converts a ConstantInteger32 operand into its constant value, or
 // MemoryOrderInvalid if the operand is not a ConstantInteger32.
 inline uint64_t getConstantMemoryOrder(Operand *Opnd) {
@@ skipping 12 matching lines @@
     Src0 = LoadSrc;
     return true;
   }
   if (Src0 != LoadDest && Src1 == LoadDest) {
     Src1 = LoadSrc;
     return true;
   }
   return false;
 }
 
-template <class Machine> void TargetX86Base<Machine>::doLoadOpt() {
+template <typename TraitsType> void TargetX86Base<TraitsType>::doLoadOpt() {
   for (CfgNode *Node : Func->getNodes()) {
     Context.init(Node);
     while (!Context.atEnd()) {
       Variable *LoadDest = nullptr;
       Operand *LoadSrc = nullptr;
       Inst *CurInst = Context.getCur();
       Inst *Next = Context.getNextInst();
       // Determine whether the current instruction is a Load instruction or
       // equivalent.
       if (auto *Load = llvm::dyn_cast<InstLoad>(CurInst)) {
@@ skipping 68 matching lines @@
           NewInst->spliceLivenessInfo(Next, CurInst);
         }
       }
       Context.advanceCur();
       Context.advanceNext();
     }
   }
   Func->dump("After load optimization");
 }
 
-template <class Machine>
-bool TargetX86Base<Machine>::doBranchOpt(Inst *I, const CfgNode *NextNode) {
-  if (auto *Br = llvm::dyn_cast<typename Traits::Insts::Br>(I)) {
+template <typename TraitsType>
+bool TargetX86Base<TraitsType>::doBranchOpt(Inst *I, const CfgNode *NextNode) {
+  if (auto *Br = llvm::dyn_cast<InstX86Br>(I)) {
     return Br->optimizeBranch(NextNode);
   }
   return false;
 }
 
-template <class Machine>
-Variable *TargetX86Base<Machine>::getPhysicalRegister(SizeT RegNum, Type Ty) {
+template <typename TraitsType>
+Variable *TargetX86Base<TraitsType>::getPhysicalRegister(SizeT RegNum,
+                                                         Type Ty) {
   if (Ty == IceType_void)
     Ty = IceType_i32;
   if (PhysicalRegisters[Ty].empty())
     PhysicalRegisters[Ty].resize(Traits::RegisterSet::Reg_NUM);
   assert(RegNum < PhysicalRegisters[Ty].size());
   Variable *Reg = PhysicalRegisters[Ty][RegNum];
   if (Reg == nullptr) {
     Reg = Func->makeVariable(Ty);
     Reg->setRegNum(RegNum);
     PhysicalRegisters[Ty][RegNum] = Reg;
     // Specially mark a named physical register as an "argument" so that it is
     // considered live upon function entry.  Otherwise it's possible to get
     // liveness validation errors for saving callee-save registers.
     Func->addImplicitArg(Reg);
     // Don't bother tracking the live range of a named physical register.
     Reg->setIgnoreLiveness();
   }
   assert(Traits::getGprForType(Ty, RegNum) == static_cast<int32_t>(RegNum));
   return Reg;
 }
 
-template <class Machine>
-IceString TargetX86Base<Machine>::getRegName(SizeT RegNum, Type Ty) const {
+template <typename TraitsType>
+IceString TargetX86Base<TraitsType>::getRegName(SizeT RegNum, Type Ty) const {
   return Traits::getRegName(Traits::getGprForType(Ty, RegNum));
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::emitVariable(const Variable *Var) const {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::emitVariable(const Variable *Var) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   if (Var->hasReg()) {
     Str << "%" << getRegName(Var->getRegNum(), Var->getType());
     return;
   }
   if (Var->mustHaveReg()) {
     llvm_unreachable("Infinite-weight Variable has no register assigned");
   }
@@ skipping 10 matching lines @@
     if (DecorateAsm) {
       Str << Var->getSymbolicStackOffset(Func);
     } else {
       Str << Offset;
     }
   }
   const Type FrameSPTy = Traits::WordType;
   Str << "(%" << getRegName(BaseRegNum, FrameSPTy) << ")";
 }
 
-template <class Machine>
-typename TargetX86Base<Machine>::Traits::Address
-TargetX86Base<Machine>::stackVarToAsmOperand(const Variable *Var) const {
+template <typename TraitsType>
+typename TargetX86Base<TraitsType>::X86Address
+TargetX86Base<TraitsType>::stackVarToAsmOperand(const Variable *Var) const {
   if (Var->hasReg())
     llvm_unreachable("Stack Variable has a register assigned");
   if (Var->mustHaveReg()) {
     llvm_unreachable("Infinite-weight Variable has no register assigned");
   }
   int32_t Offset = Var->getStackOffset();
   int32_t BaseRegNum = Var->getBaseRegNum();
   if (Var->getBaseRegNum() == Variable::NoRegister)
     BaseRegNum = getFrameOrStackReg();
-  return typename Traits::Address(Traits::getEncodedGPR(BaseRegNum), Offset,
-                                  AssemblerFixup::NoFixup);
+  return X86Address(Traits::getEncodedGPR(BaseRegNum), Offset,
+                    AssemblerFixup::NoFixup);
 }
 
 /// Helper function for addProlog().
 ///
 /// This assumes Arg is an argument passed on the stack. This sets the frame
 /// offset for Arg and updates InArgsSizeBytes according to Arg's width. For an
 /// I64 arg that has been split into Lo and Hi components, it calls itself
 /// recursively on the components, taking care to handle Lo first because of the
 /// little-endian architecture. Lastly, this function generates an instruction
 /// to copy Arg into its assigned register if applicable.
-template <class Machine>
-void TargetX86Base<Machine>::finishArgumentLowering(Variable *Arg,
-                                                    Variable *FramePtr,
-                                                    size_t BasicFrameOffset,
-                                                    size_t StackAdjBytes,
-                                                    size_t &InArgsSizeBytes) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::finishArgumentLowering(
+    Variable *Arg, Variable *FramePtr, size_t BasicFrameOffset,
+    size_t StackAdjBytes, size_t &InArgsSizeBytes) {
   if (!Traits::Is64Bit) {
     if (auto *Arg64On32 = llvm::dyn_cast<Variable64On32>(Arg)) {
       Variable *Lo = Arg64On32->getLo();
       Variable *Hi = Arg64On32->getHi();
       finishArgumentLowering(Lo, FramePtr, BasicFrameOffset, StackAdjBytes,
                              InArgsSizeBytes);
       finishArgumentLowering(Hi, FramePtr, BasicFrameOffset, StackAdjBytes,
                              InArgsSizeBytes);
       return;
     }
   }
   Type Ty = Arg->getType();
   if (isVectorType(Ty)) {
     InArgsSizeBytes = Traits::applyStackAlignment(InArgsSizeBytes);
   }
   Arg->setStackOffset(BasicFrameOffset + InArgsSizeBytes);
   InArgsSizeBytes += typeWidthInBytesOnStack(Ty);
   if (Arg->hasReg()) {
     assert(Ty != IceType_i64 || Traits::Is64Bit);
-    auto *Mem = Traits::X86OperandMem::create(
+    auto *Mem = X86OperandMem::create(
         Func, Ty, FramePtr,
         Ctx->getConstantInt32(Arg->getStackOffset() + StackAdjBytes));
     if (isVectorType(Arg->getType())) {
       _movp(Arg, Mem);
     } else {
       _mov(Arg, Mem);
     }
-    // This argument-copying instruction uses an explicit Traits::X86OperandMem
+    // This argument-copying instruction uses an explicit X86OperandMem
     // operand instead of a Variable, so its fill-from-stack operation has to
     // be tracked separately for statistics.
     Ctx->statsUpdateFills();
   }
 }
 
-template <class Machine> Type TargetX86Base<Machine>::stackSlotType() {
+template <typename TraitsType> Type TargetX86Base<TraitsType>::stackSlotType() {
   return Traits::WordType;
 }
 
-template <class Machine>
+template <typename TraitsType>
 template <typename T>
 typename std::enable_if<!T::Is64Bit, Operand>::type *
-TargetX86Base<Machine>::loOperand(Operand *Operand) {
+TargetX86Base<TraitsType>::loOperand(Operand *Operand) {
   assert(Operand->getType() == IceType_i64 ||
          Operand->getType() == IceType_f64);
   if (Operand->getType() != IceType_i64 && Operand->getType() != IceType_f64)
     return Operand;
   if (auto *Var64On32 = llvm::dyn_cast<Variable64On32>(Operand))
     return Var64On32->getLo();
   if (auto *Const = llvm::dyn_cast<ConstantInteger64>(Operand)) {
     auto *ConstInt = llvm::dyn_cast<ConstantInteger32>(
         Ctx->getConstantInt32(static_cast<int32_t>(Const->getValue())));
     // Check if we need to blind/pool the constant.
     return legalize(ConstInt);
   }
-  if (auto *Mem = llvm::dyn_cast<typename Traits::X86OperandMem>(Operand)) {
-    auto *MemOperand = Traits::X86OperandMem::create(
+  if (auto *Mem = llvm::dyn_cast<X86OperandMem>(Operand)) {
+    auto *MemOperand = X86OperandMem::create(
         Func, IceType_i32, Mem->getBase(), Mem->getOffset(), Mem->getIndex(),
         Mem->getShift(), Mem->getSegmentRegister());
     // Test if we should randomize or pool the offset, if so randomize it or
     // pool it then create mem operand with the blinded/pooled constant.
     // Otherwise, return the mem operand as ordinary mem operand.
     return legalize(MemOperand);
   }
   llvm_unreachable("Unsupported operand type");
   return nullptr;
 }
 
-template <class Machine>
+template <typename TraitsType>
 template <typename T>
 typename std::enable_if<!T::Is64Bit, Operand>::type *
-TargetX86Base<Machine>::hiOperand(Operand *Operand) {
+TargetX86Base<TraitsType>::hiOperand(Operand *Operand) {
   assert(Operand->getType() == IceType_i64 ||
          Operand->getType() == IceType_f64);
   if (Operand->getType() != IceType_i64 && Operand->getType() != IceType_f64)
     return Operand;
   if (auto *Var64On32 = llvm::dyn_cast<Variable64On32>(Operand))
     return Var64On32->getHi();
   if (auto *Const = llvm::dyn_cast<ConstantInteger64>(Operand)) {
     auto *ConstInt = llvm::dyn_cast<ConstantInteger32>(
         Ctx->getConstantInt32(static_cast<int32_t>(Const->getValue() >> 32)));
     // Check if we need to blind/pool the constant.
     return legalize(ConstInt);
   }
-  if (auto *Mem = llvm::dyn_cast<typename Traits::X86OperandMem>(Operand)) {
+  if (auto *Mem = llvm::dyn_cast<X86OperandMem>(Operand)) {
     Constant *Offset = Mem->getOffset();
     if (Offset == nullptr) {
       Offset = Ctx->getConstantInt32(4);
     } else if (auto *IntOffset = llvm::dyn_cast<ConstantInteger32>(Offset)) {
       Offset = Ctx->getConstantInt32(4 + IntOffset->getValue());
     } else if (auto *SymOffset = llvm::dyn_cast<ConstantRelocatable>(Offset)) {
       assert(!Utils::WouldOverflowAdd(SymOffset->getOffset(), 4));
       Offset =
           Ctx->getConstantSym(4 + SymOffset->getOffset(), SymOffset->getName(),
                               SymOffset->getSuppressMangling());
     }
-    auto *MemOperand = Traits::X86OperandMem::create(
+    auto *MemOperand = X86OperandMem::create(
         Func, IceType_i32, Mem->getBase(), Offset, Mem->getIndex(),
         Mem->getShift(), Mem->getSegmentRegister());
     // Test if the Offset is an eligible i32 constants for randomization and
     // pooling. Blind/pool it if it is. Otherwise return as oridinary mem
     // operand.
     return legalize(MemOperand);
   }
   llvm_unreachable("Unsupported operand type");
   return nullptr;
 }
 
-template <class Machine>
+template <typename TraitsType>
 llvm::SmallBitVector
-TargetX86Base<Machine>::getRegisterSet(RegSetMask Include,
-                                       RegSetMask Exclude) const {
+TargetX86Base<TraitsType>::getRegisterSet(RegSetMask Include,
+                                          RegSetMask Exclude) const {
   return Traits::getRegisterSet(Include, Exclude);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerAlloca(const InstAlloca *Inst) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerAlloca(const InstAlloca *Inst) {
   // Conservatively require the stack to be aligned. Some stack adjustment
   // operations implemented below assume that the stack is aligned before the
   // alloca. All the alloca code ensures that the stack alignment is preserved
   // after the alloca. The stack alignment restriction can be relaxed in some
   // cases.
   NeedsStackAlignment = true;
 
   // For default align=0, set it to the real value 1, to avoid any
   // bit-manipulation problems below.
   const uint32_t AlignmentParam = std::max(1u, Inst->getAlignInBytes());
@@ skipping 45 matching lines @@
       _mov(T, TotalSize);
     }
     _add(T, Ctx->getConstantInt32(Alignment - 1));
     _and(T, Ctx->getConstantInt32(-Alignment));
     _sub(esp, T);
   }
   // Add enough to the returned address to account for the out args area.
   uint32_t OutArgsSize = maxOutArgsSizeBytes();
   if (OutArgsSize > 0) {
     Variable *T = makeReg(IceType_i32);
-    typename Traits::X86OperandMem *CalculateOperand =
-        Traits::X86OperandMem::create(
-            Func, IceType_i32, esp,
-            Ctx->getConstantInt(IceType_i32, OutArgsSize));
+    auto *CalculateOperand = X86OperandMem::create(
+        Func, IceType_i32, esp, Ctx->getConstantInt(IceType_i32, OutArgsSize));
     _lea(T, CalculateOperand);
     _mov(Dest, T);
   } else {
     _mov(Dest, esp);
   }
 }
 
 /// Strength-reduce scalar integer multiplication by a constant (for i32 or
 /// narrower) for certain constants. The lea instruction can be used to multiply
 /// by 3, 5, or 9, and the lsh instruction can be used to multiply by powers of
 /// 2. These can be combined such that e.g. multiplying by 100 can be done as 2
 /// lea-based multiplies by 5, combined with left-shifting by 2.
-template <class Machine>
-bool TargetX86Base<Machine>::optimizeScalarMul(Variable *Dest, Operand *Src0,
-                                               int32_t Src1) {
+template <typename TraitsType>
+bool TargetX86Base<TraitsType>::optimizeScalarMul(Variable *Dest, Operand *Src0,
+                                                  int32_t Src1) {
   // Disable this optimization for Om1 and O0, just to keep things simple
   // there.
   if (Ctx->getFlags().getOptLevel() < Opt_1)
     return false;
   Type Ty = Dest->getType();
   Variable *T = nullptr;
   if (Src1 == -1) {
     _mov(T, Src0);
     _neg(T);
     _mov(Dest, T);
@@ skipping 46 matching lines @@
     return false;
   // Limit the number of lea/shl operations for a single multiply, to a
   // somewhat arbitrary choice of 3.
   constexpr uint32_t MaxOpsForOptimizedMul = 3;
   if (CountOps > MaxOpsForOptimizedMul)
     return false;
   _mov(T, Src0);
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   for (uint32_t i = 0; i < Count9; ++i) {
     constexpr uint16_t Shift = 3; // log2(9-1)
-    _lea(T,
-         Traits::X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
+    _lea(T, X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
   }
   for (uint32_t i = 0; i < Count5; ++i) {
     constexpr uint16_t Shift = 2; // log2(5-1)
-    _lea(T,
-         Traits::X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
+    _lea(T, X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
   }
   for (uint32_t i = 0; i < Count3; ++i) {
     constexpr uint16_t Shift = 1; // log2(3-1)
-    _lea(T,
-         Traits::X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
+    _lea(T, X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
   }
   if (Count2) {
     _shl(T, Ctx->getConstantInt(Ty, Count2));
   }
   if (Src1IsNegative)
     _neg(T);
   _mov(Dest, T);
   return true;
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerShift64(InstArithmetic::OpKind Op,
-                                          Operand *Src0Lo, Operand *Src0Hi,
-                                          Operand *Src1Lo, Variable *DestLo,
-                                          Variable *DestHi) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerShift64(InstArithmetic::OpKind Op,
+                                             Operand *Src0Lo, Operand *Src0Hi,
+                                             Operand *Src1Lo, Variable *DestLo,
+                                             Variable *DestHi) {
   // TODO: Refactor the similarities between Shl, Lshr, and Ashr.
   Variable *T_1 = nullptr, *T_2 = nullptr, *T_3 = nullptr;
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   Constant *SignExtend = Ctx->getConstantInt32(0x1f);
   if (auto *ConstantShiftAmount = llvm::dyn_cast<ConstantInteger32>(Src1Lo)) {
     uint32_t ShiftAmount = ConstantShiftAmount->getValue();
     if (ShiftAmount > 32) {
       Constant *ReducedShift = Ctx->getConstantInt32(ShiftAmount - 32);
       switch (Op) {
       default:
@@ skipping 108 matching lines @@
       }
       // COMMON SUFFIX OF: a=b SHIFT_OP c ==>
       //   a.lo = t2
       //   a.hi = t3
       _mov(DestLo, T_2);
       _mov(DestHi, T_3);
     }
   } else {
     // NON-CONSTANT CASES.
     Constant *BitTest = Ctx->getConstantInt32(0x20);
-    typename Traits::Insts::Label *Label =
-        Traits::Insts::Label::create(Func, this);
+    InstX86Label *Label = InstX86Label::create(Func, this);
     // COMMON PREFIX OF: a=b SHIFT_OP c ==>
     //   t1:ecx = c.lo & 0xff
     //   t2 = b.lo
     //   t3 = b.hi
     T_1 = copyToReg8(Src1Lo, Traits::RegisterSet::Reg_cl);
     _mov(T_2, Src0Lo);
     _mov(T_3, Src0Hi);
     switch (Op) {
     default:
       assert(0 && "non-shift op");
@@ skipping 59 matching lines @@
     // COMMON SUFFIX OF: a=b SHIFT_OP c ==>
     // L1:
     //   a.lo = t2
     //   a.hi = t3
     Context.insert(Label);
     _mov(DestLo, T_2);
     _mov(DestHi, T_3);
   }
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerArithmetic(const InstArithmetic *Inst) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerArithmetic(const InstArithmetic *Inst) {
   Variable *Dest = Inst->getDest();
   if (Dest->isRematerializable()) {
     Context.insert<InstFakeDef>(Dest);
     return;
   }
   Type Ty = Dest->getType();
   Operand *Src0 = legalize(Inst->getSrc(0));
   Operand *Src1 = legalize(Inst->getSrc(1));
   if (Inst->isCommutative()) {
     uint32_t SwapCount = 0;
@@ skipping 131 matching lines @@
     case InstArithmetic::Srem:
       llvm_unreachable("Call-helper-involved instruction for i64 type \
                        should have already been handled before");
       break;
     }
     return;
   }
   if (isVectorType(Ty)) {
     // TODO: Trap on integer divide and integer modulo by zero. See:
     // https://code.google.com/p/nativeclient/issues/detail?id=3899
-    if (llvm::isa<typename Traits::X86OperandMem>(Src1))
+    if (llvm::isa<X86OperandMem>(Src1))
       Src1 = legalizeToReg(Src1);
     switch (Inst->getOp()) {
     case InstArithmetic::_num:
       llvm_unreachable("Unknown arithmetic operator");
       break;
     case InstArithmetic::Add: {
       Variable *T = makeReg(Ty);
       _movp(T, Src0);
       _padd(T, Src1);
       _movp(Dest, T);
@@ skipping 398 matching lines @@
     _mov(T, Src0);
     _divss(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Frem:
     llvm::report_fatal_error("Helper call was expected");
     break;
   }
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerAssign(const InstAssign *Inst) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerAssign(const InstAssign *Inst) {
   Variable *Dest = Inst->getDest();
   if (Dest->isRematerializable()) {
     Context.insert<InstFakeDef>(Dest);
     return;
   }
   Operand *Src = Inst->getSrc(0);
   assert(Dest->getType() == Src->getType());
   lowerMove(Dest, Src, false);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerBr(const InstBr *Br) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerBr(const InstBr *Br) {
   if (Br->isUnconditional()) {
     _br(Br->getTargetUnconditional());
     return;
   }
   Operand *Cond = Br->getCondition();
 
   // Handle folding opportunities.
   if (const Inst *Producer = FoldingInfo.getProducerFor(Cond)) {
     assert(Producer->isDeleted());
     switch (BoolFolding::getProducerKind(Producer)) {
@@ skipping 13 matching lines @@
       return;
     }
     }
   }
   Operand *Src0 = legalize(Cond, Legal_Reg | Legal_Mem);
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   _cmp(Src0, Zero);
   _br(Traits::Cond::Br_ne, Br->getTargetTrue(), Br->getTargetFalse());
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerCast(const InstCast *Inst) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerCast(const InstCast *Inst) {
   // a = cast(b) ==> t=cast(b); a=t; (link t->b, link a->t, no overlap)
   InstCast::OpKind CastKind = Inst->getCastKind();
   Variable *Dest = Inst->getDest();
   Type DestTy = Dest->getType();
   switch (CastKind) {
   default:
     Func->setError("Cast type not supported");
     return;
   case InstCast::Sext: {
     // Src0RM is the source operand legalized to physical register or memory,
@@ skipping 157 matching lines @@
     Variable *T = makeReg(DestTy);
     _cvt(T, Src0RM, Traits::Insts::Cvt::Float2float);
     _mov(Dest, T);
     break;
   }
   case InstCast::Fptosi:
     if (isVectorType(DestTy)) {
       assert(DestTy == IceType_v4i32 &&
              Inst->getSrc(0)->getType() == IceType_v4f32);
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
-      if (llvm::isa<typename Traits::X86OperandMem>(Src0RM))
+      if (llvm::isa<X86OperandMem>(Src0RM))
         Src0RM = legalizeToReg(Src0RM);
       Variable *T = makeReg(DestTy);
       _cvt(T, Src0RM, Traits::Insts::Cvt::Tps2dq);
       _movp(Dest, T);
     } else if (!Traits::Is64Bit && DestTy == IceType_i64) {
       llvm::report_fatal_error("Helper call was expected");
     } else {
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       // t1.i32 = cvt Src0RM; t2.dest_type = t1; Dest = t2.dest_type
       Variable *T_1 = nullptr;
@@ skipping 45 matching lines @@
       if (DestTy == IceType_i1)
         _and(T_2, Ctx->getConstantInt1(1));
       _mov(Dest, T_2);
     }
     break;
   case InstCast::Sitofp:
     if (isVectorType(DestTy)) {
       assert(DestTy == IceType_v4f32 &&
              Inst->getSrc(0)->getType() == IceType_v4i32);
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
-      if (llvm::isa<typename Traits::X86OperandMem>(Src0RM))
+      if (llvm::isa<X86OperandMem>(Src0RM))
         Src0RM = legalizeToReg(Src0RM);
       Variable *T = makeReg(DestTy);
       _cvt(T, Src0RM, Traits::Insts::Cvt::Dq2ps);
       _movp(Dest, T);
     } else if (!Traits::Is64Bit && Inst->getSrc(0)->getType() == IceType_i64) {
       llvm::report_fatal_error("Helper call was expected");
     } else {
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       // Sign-extend the operand.
       // t1.i32 = movsx Src0RM; t2 = Cvt t1.i32; Dest = t2
@@ skipping 64 matching lines @@
       Type SrcType = Src0RM->getType();
       assert((DestTy == IceType_i32 && SrcType == IceType_f32) ||
              (DestTy == IceType_f32 && SrcType == IceType_i32));
       // a.i32 = bitcast b.f32 ==>
       //   t.f32 = b.f32
       //   s.f32 = spill t.f32
       //   a.i32 = s.f32
       Variable *T = nullptr;
       // TODO: Should be able to force a spill setup by calling legalize() with
       // Legal_Mem and not Legal_Reg or Legal_Imm.
-      typename Traits::SpillVariable *SpillVar =
-          Func->makeVariable<typename Traits::SpillVariable>(SrcType);
+      SpillVariable *SpillVar = Func->makeVariable<SpillVariable>(SrcType);
       SpillVar->setLinkedTo(Dest);
       Variable *Spill = SpillVar;
       Spill->setMustNotHaveReg();
       _mov(T, Src0RM);
       _mov(Spill, T);
       _mov(Dest, Spill);
     } break;
     case IceType_i64: {
       assert(Src0->getType() == IceType_f64);
       if (Traits::Is64Bit) {
         Variable *Src0R = legalizeToReg(Src0);
         Variable *T = makeReg(IceType_i64);
         _movd(T, Src0R);
         _mov(Dest, T);
       } else {
         Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
         // a.i64 = bitcast b.f64 ==>
         //   s.f64 = spill b.f64
         //   t_lo.i32 = lo(s.f64)
         //   a_lo.i32 = t_lo.i32
         //   t_hi.i32 = hi(s.f64)
         //   a_hi.i32 = t_hi.i32
         Operand *SpillLo, *SpillHi;
         if (auto *Src0Var = llvm::dyn_cast<Variable>(Src0RM)) {
-          typename Traits::SpillVariable *SpillVar =
-              Func->makeVariable<typename Traits::SpillVariable>(IceType_f64);
+          SpillVariable *SpillVar =
+              Func->makeVariable<SpillVariable>(IceType_f64);
           SpillVar->setLinkedTo(Src0Var);
           Variable *Spill = SpillVar;
           Spill->setMustNotHaveReg();
           _movq(Spill, Src0RM);
           SpillLo = Traits::VariableSplit::create(Func, Spill,
                                                   Traits::VariableSplit::Low);
           SpillHi = Traits::VariableSplit::create(Func, Spill,
                                                   Traits::VariableSplit::High);
         } else {
           SpillLo = loOperand(Src0RM);
@@ skipping 13 matching lines @@
     } break;
     case IceType_f64: {
       assert(Src0->getType() == IceType_i64);
       if (Traits::Is64Bit) {
         Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
         Variable *T = makeReg(IceType_f64);
         _movd(T, Src0RM);
         _mov(Dest, T);
       } else {
         Src0 = legalize(Src0);
-        if (llvm::isa<typename Traits::X86OperandMem>(Src0)) {
+        if (llvm::isa<X86OperandMem>(Src0)) {
           Variable *T = Func->makeVariable(DestTy);
           _movq(T, Src0);
           _movq(Dest, T);
           break;
         }
         // a.f64 = bitcast b.i64 ==>
         //   t_lo.i32 = b_lo.i32
         //   FakeDef(s.f64)
         //   lo(s.f64) = t_lo.i32
         //   t_hi.i32 = b_hi.i32
         //   hi(s.f64) = t_hi.i32
         //   a.f64 = s.f64
-        typename Traits::SpillVariable *SpillVar =
-            Func->makeVariable<typename Traits::SpillVariable>(IceType_f64);
+        SpillVariable *SpillVar =
+            Func->makeVariable<SpillVariable>(IceType_f64);
         SpillVar->setLinkedTo(Dest);
         Variable *Spill = SpillVar;
         Spill->setMustNotHaveReg();
 
         Variable *T_Lo = nullptr, *T_Hi = nullptr;
         auto *SpillLo = Traits::VariableSplit::create(
             Func, Spill, Traits::VariableSplit::Low);
         auto *SpillHi = Traits::VariableSplit::create(
             Func, Spill, Traits::VariableSplit::High);
         _mov(T_Lo, loOperand(Src0));
@@ skipping 18 matching lines @@
     case IceType_v4i32:
     case IceType_v4f32: {
       _movp(Dest, legalizeToReg(Src0));
     } break;
     }
     break;
   }
   }
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerExtractElement(
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerExtractElement(
     const InstExtractElement *Inst) {
   Operand *SourceVectNotLegalized = Inst->getSrc(0);
   ConstantInteger32 *ElementIndex =
       llvm::dyn_cast<ConstantInteger32>(Inst->getSrc(1));
   // Only constant indices are allowed in PNaCl IR.
   assert(ElementIndex);
 
   unsigned Index = ElementIndex->getValue();
   Type Ty = SourceVectNotLegalized->getType();
   Type ElementTy = typeElementType(Ty);
@@ skipping 41 matching lines @@
     // Spill the value to a stack slot and do the extraction in memory.
     //
     // TODO(wala): use legalize(SourceVectNotLegalized, Legal_Mem) when support
     // for legalizing to mem is implemented.
     Variable *Slot = Func->makeVariable(Ty);
     Slot->setMustNotHaveReg();
     _movp(Slot, legalizeToReg(SourceVectNotLegalized));
 
     // Compute the location of the element in memory.
     unsigned Offset = Index * typeWidthInBytes(InVectorElementTy);
-    typename Traits::X86OperandMem *Loc =
+    X86OperandMem *Loc =
         getMemoryOperandForStackSlot(InVectorElementTy, Slot, Offset);
     _mov(ExtractedElementR, Loc);
   }
 
   if (ElementTy == IceType_i1) {
     // Truncate extracted integers to i1s if necessary.
     Variable *T = makeReg(IceType_i1);
     InstCast *Cast =
         InstCast::create(Func, InstCast::Trunc, T, ExtractedElementR);
     lowerCast(Cast);
     ExtractedElementR = T;
   }
 
   // Copy the element to the destination.
   Variable *Dest = Inst->getDest();
   _mov(Dest, ExtractedElementR);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerFcmp(const InstFcmp *Fcmp) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerFcmp(const InstFcmp *Fcmp) {
   Variable *Dest = Fcmp->getDest();
 
   if (isVectorType(Dest->getType())) {
     lowerFcmpVector(Fcmp);
   } else {
     constexpr Inst *Consumer = nullptr;
     lowerFcmpAndConsumer(Fcmp, Consumer);
   }
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerFcmpAndConsumer(const InstFcmp *Fcmp,
-                                                  const Inst *Consumer) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerFcmpAndConsumer(const InstFcmp *Fcmp,
+                                                     const Inst *Consumer) {
   Operand *Src0 = Fcmp->getSrc(0);
   Operand *Src1 = Fcmp->getSrc(1);
   Variable *Dest = Fcmp->getDest();
 
   if (isVectorType(Dest->getType()))
     llvm::report_fatal_error("Vector compare/branch cannot be folded");
 
   if (Consumer != nullptr) {
     if (auto *Select = llvm::dyn_cast<InstSelect>(Consumer)) {
       if (lowerOptimizeFcmpSelect(Fcmp, Select))
@@ skipping 31 matching lines @@
       assert(Traits::TableFcmp[Index].Default);
       setccOrConsumer(Traits::TableFcmp[Index].C1, Dest, Consumer);
       return;
     }
   }
   int32_t IntDefault = Traits::TableFcmp[Index].Default;
   if (Consumer == nullptr) {
     Constant *Default = Ctx->getConstantInt(Dest->getType(), IntDefault);
     _mov(Dest, Default);
     if (HasC1) {
-      typename Traits::Insts::Label *Label =
-          Traits::Insts::Label::create(Func, this);
+      InstX86Label *Label = InstX86Label::create(Func, this);
       _br(Traits::TableFcmp[Index].C1, Label);
       if (HasC2) {
         _br(Traits::TableFcmp[Index].C2, Label);
       }
       Constant *NonDefault = Ctx->getConstantInt(Dest->getType(), !IntDefault);
       _redefined(_mov(Dest, NonDefault));
       Context.insert(Label);
     }
     return;
   }
@@ skipping 14 matching lines @@
     return;
   }
   if (auto *Select = llvm::dyn_cast<InstSelect>(Consumer)) {
     Operand *SrcT = Select->getTrueOperand();
     Operand *SrcF = Select->getFalseOperand();
     Variable *SelectDest = Select->getDest();
     if (IntDefault != 0)
       std::swap(SrcT, SrcF);
     lowerMove(SelectDest, SrcF, false);
     if (HasC1) {
-      typename Traits::Insts::Label *Label =
-          Traits::Insts::Label::create(Func, this);
+      InstX86Label *Label = InstX86Label::create(Func, this);
       _br(Traits::TableFcmp[Index].C1, Label);
       if (HasC2) {
         _br(Traits::TableFcmp[Index].C2, Label);
       }
       static constexpr bool IsRedefinition = true;
       lowerMove(SelectDest, SrcT, IsRedefinition);
       Context.insert(Label);
     }
     return;
   }
   llvm::report_fatal_error("Unexpected consumer type");
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerFcmpVector(const InstFcmp *Fcmp) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerFcmpVector(const InstFcmp *Fcmp) {
   Operand *Src0 = Fcmp->getSrc(0);
   Operand *Src1 = Fcmp->getSrc(1);
   Variable *Dest = Fcmp->getDest();
 
   if (!isVectorType(Dest->getType()))
     llvm::report_fatal_error("Expected vector compare");
 
   InstFcmp::FCond Condition = Fcmp->getCondition();
   size_t Index = static_cast<size_t>(Condition);
   assert(Index < Traits::TableFcmpSize);
 
   if (Traits::TableFcmp[Index].SwapVectorOperands)
     std::swap(Src0, Src1);
 
   Variable *T = nullptr;
 
   if (Condition == InstFcmp::True) {
     // makeVectorOfOnes() requires an integer vector type.
     T = makeVectorOfMinusOnes(IceType_v4i32);
   } else if (Condition == InstFcmp::False) {
     T = makeVectorOfZeros(Dest->getType());
   } else {
     Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
     Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
-    if (llvm::isa<typename Traits::X86OperandMem>(Src1RM))
+    if (llvm::isa<X86OperandMem>(Src1RM))
       Src1RM = legalizeToReg(Src1RM);
 
     switch (Condition) {
     default: {
-      typename Traits::Cond::CmppsCond Predicate =
-          Traits::TableFcmp[Index].Predicate;
+      CmppsCond Predicate = Traits::TableFcmp[Index].Predicate;
       assert(Predicate != Traits::Cond::Cmpps_Invalid);
       T = makeReg(Src0RM->getType());
       _movp(T, Src0RM);
       _cmpps(T, Src1RM, Predicate);
     } break;
     case InstFcmp::One: {
       // Check both unequal and ordered.
       T = makeReg(Src0RM->getType());
       Variable *T2 = makeReg(Src0RM->getType());
       _movp(T, Src0RM);
@@ skipping 21 matching lines @@
 }
 
 inline bool isZero(const Operand *Opnd) {
   if (auto *C64 = llvm::dyn_cast<ConstantInteger64>(Opnd))
     return C64->getValue() == 0;
   if (auto *C32 = llvm::dyn_cast<ConstantInteger32>(Opnd))
     return C32->getValue() == 0;
   return false;
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerIcmpAndConsumer(const InstIcmp *Icmp,
-                                                  const Inst *Consumer) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerIcmpAndConsumer(const InstIcmp *Icmp,
+                                                     const Inst *Consumer) {
   Operand *Src0 = legalize(Icmp->getSrc(0));
   Operand *Src1 = legalize(Icmp->getSrc(1));
   Variable *Dest = Icmp->getDest();
 
   if (isVectorType(Dest->getType()))
     llvm::report_fatal_error("Vector compare/branch cannot be folded");
 
   if (!Traits::Is64Bit && Src0->getType() == IceType_i64) {
     lowerIcmp64(Icmp, Consumer);
     return;
@@ skipping 11 matching lines @@
       movOrConsumer(false, Dest, Consumer);
       return;
     }
   }
   Operand *Src0RM = legalizeSrc0ForCmp(Src0, Src1);
   _cmp(Src0RM, Src1);
   setccOrConsumer(Traits::getIcmp32Mapping(Icmp->getCondition()), Dest,
                   Consumer);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerIcmpVector(const InstIcmp *Icmp) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerIcmpVector(const InstIcmp *Icmp) {
   Operand *Src0 = legalize(Icmp->getSrc(0));
   Operand *Src1 = legalize(Icmp->getSrc(1));
   Variable *Dest = Icmp->getDest();
 
   if (!isVectorType(Dest->getType()))
     llvm::report_fatal_error("Expected a vector compare");
 
   Type Ty = Src0->getType();
   // Promote i1 vectors to 128 bit integer vector types.
   if (typeElementType(Ty) == IceType_i1) {
@@ skipping 41 matching lines @@
     Src0RM = T0;
     Src1RM = T1;
   }
 
   Variable *T = makeReg(Ty);
   switch (Condition) {
   default:
     llvm_unreachable("unexpected condition");
     break;
   case InstIcmp::Eq: {
-    if (llvm::isa<typename Traits::X86OperandMem>(Src1RM))
+    if (llvm::isa<X86OperandMem>(Src1RM))
       Src1RM = legalizeToReg(Src1RM);
     _movp(T, Src0RM);
     _pcmpeq(T, Src1RM);
   } break;
   case InstIcmp::Ne: {
-    if (llvm::isa<typename Traits::X86OperandMem>(Src1RM))
+    if (llvm::isa<X86OperandMem>(Src1RM))
       Src1RM = legalizeToReg(Src1RM);
     _movp(T, Src0RM);
     _pcmpeq(T, Src1RM);
     Variable *MinusOne = makeVectorOfMinusOnes(Ty);
     _pxor(T, MinusOne);
   } break;
   case InstIcmp::Ugt:
   case InstIcmp::Sgt: {
-    if (llvm::isa<typename Traits::X86OperandMem>(Src1RM))
+    if (llvm::isa<X86OperandMem>(Src1RM))
       Src1RM = legalizeToReg(Src1RM);
     _movp(T, Src0RM);
     _pcmpgt(T, Src1RM);
   } break;
   case InstIcmp::Uge:
   case InstIcmp::Sge: {
     // !(Src1RM > Src0RM)
-    if (llvm::isa<typename Traits::X86OperandMem>(Src0RM))
+    if (llvm::isa<X86OperandMem>(Src0RM))
       Src0RM = legalizeToReg(Src0RM);
     _movp(T, Src1RM);
     _pcmpgt(T, Src0RM);
     Variable *MinusOne = makeVectorOfMinusOnes(Ty);
     _pxor(T, MinusOne);
   } break;
   case InstIcmp::Ult:
   case InstIcmp::Slt: {
-    if (llvm::isa<typename Traits::X86OperandMem>(Src0RM))
+    if (llvm::isa<X86OperandMem>(Src0RM))
       Src0RM = legalizeToReg(Src0RM);
     _movp(T, Src1RM);
     _pcmpgt(T, Src0RM);
   } break;
   case InstIcmp::Ule:
   case InstIcmp::Sle: {
     // !(Src0RM > Src1RM)
-    if (llvm::isa<typename Traits::X86OperandMem>(Src1RM))
+    if (llvm::isa<X86OperandMem>(Src1RM))
       Src1RM = legalizeToReg(Src1RM);
     _movp(T, Src0RM);
     _pcmpgt(T, Src1RM);
     Variable *MinusOne = makeVectorOfMinusOnes(Ty);
     _pxor(T, MinusOne);
   } break;
   }
 
   _movp(Dest, T);
   eliminateNextVectorSextInstruction(Dest);
 }
 
-template <typename Machine>
+template <typename TraitsType>
 template <typename T>
 typename std::enable_if<!T::Is64Bit, void>::type
-TargetX86Base<Machine>::lowerIcmp64(const InstIcmp *Icmp,
-                                    const Inst *Consumer) {
+TargetX86Base<TraitsType>::lowerIcmp64(const InstIcmp *Icmp,
+                                       const Inst *Consumer) {
   // a=icmp cond, b, c ==> cmp b,c; a=1; br cond,L1; FakeUse(a); a=0; L1:
   Operand *Src0 = legalize(Icmp->getSrc(0));
   Operand *Src1 = legalize(Icmp->getSrc(1));
   Variable *Dest = Icmp->getDest();
   InstIcmp::ICond Condition = Icmp->getCondition();
   size_t Index = static_cast<size_t>(Condition);
   assert(Index < Traits::TableIcmp64Size);
   Operand *Src0LoRM = nullptr;
   Operand *Src0HiRM = nullptr;
   // Legalize the portions of Src0 that are going to be needed.
@@ skipping 74 matching lines @@
     case InstIcmp::Sle:
       break;
     }
   }
   // Handle general compares.
   Operand *Src1LoRI = legalize(loOperand(Src1), Legal_Reg | Legal_Imm);
   Operand *Src1HiRI = legalize(hiOperand(Src1), Legal_Reg | Legal_Imm);
   if (Consumer == nullptr) {
     Constant *Zero = Ctx->getConstantInt(Dest->getType(), 0);
     Constant *One = Ctx->getConstantInt(Dest->getType(), 1);
-    typename Traits::Insts::Label *LabelFalse =
-        Traits::Insts::Label::create(Func, this);
-    typename Traits::Insts::Label *LabelTrue =
-        Traits::Insts::Label::create(Func, this);
+    InstX86Label *LabelFalse = InstX86Label::create(Func, this);
+    InstX86Label *LabelTrue = InstX86Label::create(Func, this);
     _mov(Dest, One);
     _cmp(Src0HiRM, Src1HiRI);
     if (Traits::TableIcmp64[Index].C1 != Traits::Cond::Br_None)
       _br(Traits::TableIcmp64[Index].C1, LabelTrue);
     if (Traits::TableIcmp64[Index].C2 != Traits::Cond::Br_None)
       _br(Traits::TableIcmp64[Index].C2, LabelFalse);
     _cmp(Src0LoRM, Src1LoRI);
     _br(Traits::TableIcmp64[Index].C3, LabelTrue);
     Context.insert(LabelFalse);
     _redefined(_mov(Dest, Zero));
     Context.insert(LabelTrue);
     return;
   }
   if (const auto *Br = llvm::dyn_cast<InstBr>(Consumer)) {
     _cmp(Src0HiRM, Src1HiRI);
     if (Traits::TableIcmp64[Index].C1 != Traits::Cond::Br_None)
       _br(Traits::TableIcmp64[Index].C1, Br->getTargetTrue());
     if (Traits::TableIcmp64[Index].C2 != Traits::Cond::Br_None)
       _br(Traits::TableIcmp64[Index].C2, Br->getTargetFalse());
     _cmp(Src0LoRM, Src1LoRI);
     _br(Traits::TableIcmp64[Index].C3, Br->getTargetTrue(),
         Br->getTargetFalse());
     return;
   }
   if (auto *Select = llvm::dyn_cast<InstSelect>(Consumer)) {
     Operand *SrcT = Select->getTrueOperand();
     Operand *SrcF = Select->getFalseOperand();
     Variable *SelectDest = Select->getDest();
-    typename Traits::Insts::Label *LabelFalse =
-        Traits::Insts::Label::create(Func, this);
-    typename Traits::Insts::Label *LabelTrue =
-        Traits::Insts::Label::create(Func, this);
+    InstX86Label *LabelFalse = InstX86Label::create(Func, this);
+    InstX86Label *LabelTrue = InstX86Label::create(Func, this);
     lowerMove(SelectDest, SrcT, false);
     _cmp(Src0HiRM, Src1HiRI);
     if (Traits::TableIcmp64[Index].C1 != Traits::Cond::Br_None)
       _br(Traits::TableIcmp64[Index].C1, LabelTrue);
     if (Traits::TableIcmp64[Index].C2 != Traits::Cond::Br_None)
       _br(Traits::TableIcmp64[Index].C2, LabelFalse);
     _cmp(Src0LoRM, Src1LoRI);
     _br(Traits::TableIcmp64[Index].C3, LabelTrue);
     Context.insert(LabelFalse);
     static constexpr bool IsRedefinition = true;
     lowerMove(SelectDest, SrcF, IsRedefinition);
     Context.insert(LabelTrue);
     return;
   }
   llvm::report_fatal_error("Unexpected consumer type");
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::setccOrConsumer(
-    typename Traits::Cond::BrCond Condition, Variable *Dest,
-    const Inst *Consumer) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::setccOrConsumer(BrCond Condition,
+                                                Variable *Dest,
+                                                const Inst *Consumer) {
   if (Consumer == nullptr) {
     _setcc(Dest, Condition);
     return;
   }
   if (const auto *Br = llvm::dyn_cast<InstBr>(Consumer)) {
     _br(Condition, Br->getTargetTrue(), Br->getTargetFalse());
     return;
   }
   if (const auto *Select = llvm::dyn_cast<InstSelect>(Consumer)) {
     Operand *SrcT = Select->getTrueOperand();
     Operand *SrcF = Select->getFalseOperand();
     Variable *SelectDest = Select->getDest();
     lowerSelectMove(SelectDest, Condition, SrcT, SrcF);
     return;
   }
   llvm::report_fatal_error("Unexpected consumer type");
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::movOrConsumer(bool IcmpResult, Variable *Dest,
-                                           const Inst *Consumer) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::movOrConsumer(bool IcmpResult, Variable *Dest,
+                                              const Inst *Consumer) {
   if (Consumer == nullptr) {
     _mov(Dest, Ctx->getConstantInt(Dest->getType(), (IcmpResult ? 1 : 0)));
     return;
   }
   if (const auto *Br = llvm::dyn_cast<InstBr>(Consumer)) {
     // TODO(sehr,stichnot): This could be done with a single unconditional
     // branch instruction, but subzero doesn't know how to handle the resulting
     // control flow graph changes now.  Make it do so to eliminate mov and cmp.
     _mov(Dest, Ctx->getConstantInt(Dest->getType(), (IcmpResult ? 1 : 0)));
     _cmp(Dest, Ctx->getConstantInt(Dest->getType(), 0));
     _br(Traits::Cond::Br_ne, Br->getTargetTrue(), Br->getTargetFalse());
     return;
   }
   if (const auto *Select = llvm::dyn_cast<InstSelect>(Consumer)) {
     Operand *Src = nullptr;
     if (IcmpResult) {
       Src = legalize(Select->getTrueOperand(), Legal_Reg | Legal_Imm);
     } else {
       Src = legalize(Select->getFalseOperand(), Legal_Reg | Legal_Imm);
     }
     Variable *SelectDest = Select->getDest();
     lowerMove(SelectDest, Src, false);
     return;
   }
   llvm::report_fatal_error("Unexpected consumer type");
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerArithAndConsumer(const InstArithmetic *Arith,
-                                                   const Inst *Consumer) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerArithAndConsumer(
+    const InstArithmetic *Arith, const Inst *Consumer) {
   Variable *T = nullptr;
   Operand *Src0 = legalize(Arith->getSrc(0));
   Operand *Src1 = legalize(Arith->getSrc(1));
   Variable *Dest = Arith->getDest();
   switch (Arith->getOp()) {
   default:
     llvm_unreachable("arithmetic operator not AND or OR");
     break;
   case InstArithmetic::And:
     _mov(T, Src0);
@@ skipping 16 matching lines @@
   }
   if (const auto *Br = llvm::dyn_cast<InstBr>(Consumer)) {
     Context.insert<InstFakeUse>(T);
     Context.insert<InstFakeDef>(Dest);
     _br(Traits::Cond::Br_ne, Br->getTargetTrue(), Br->getTargetFalse());
     return;
   }
   llvm::report_fatal_error("Unexpected consumer type");
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerInsertElement(const InstInsertElement *Inst) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerInsertElement(
+    const InstInsertElement *Inst) {
   Operand *SourceVectNotLegalized = Inst->getSrc(0);
   Operand *ElementToInsertNotLegalized = Inst->getSrc(1);
   ConstantInteger32 *ElementIndex =
       llvm::dyn_cast<ConstantInteger32>(Inst->getSrc(2));
   // Only constant indices are allowed in PNaCl IR.
   assert(ElementIndex);
   unsigned Index = ElementIndex->getValue();
   assert(Index < typeNumElements(SourceVectNotLegalized->getType()));
 
   Type Ty = SourceVectNotLegalized->getType();
@@ skipping 17 matching lines @@
         legalize(ElementToInsertNotLegalized, Legal_Reg | Legal_Mem);
     Operand *SourceVectRM =
         legalize(SourceVectNotLegalized, Legal_Reg | Legal_Mem);
     Variable *T = makeReg(Ty);
     _movp(T, SourceVectRM);
     if (Ty == IceType_v4f32) {
       _insertps(T, ElementRM, Ctx->getConstantInt32(Index << 4));
     } else {
       // For the pinsrb and pinsrw instructions, when the source operand is a
       // register, it must be a full r32 register like eax, and not ax/al/ah.
-      // For filetype=asm, InstX86Pinsr<Machine>::emit() compensates for the use
+      // For filetype=asm, InstX86Pinsr<TraitsType>::emit() compensates for
+      // the use
       // of r16 and r8 by converting them through getBaseReg(), while emitIAS()
       // validates that the original and base register encodings are the same.
       if (ElementRM->getType() == IceType_i8 &&
           llvm::isa<Variable>(ElementRM)) {
         // Don't use ah/bh/ch/dh for pinsrb.
         ElementRM = copyToReg8(ElementRM);
       }
       _pinsr(T, ElementRM, Ctx->getConstantInt32(Index));
     }
     _movp(Inst->getDest(), T);
@@ skipping 64 matching lines @@
     // Spill the value to a stack slot and perform the insertion in memory.
     //
     // TODO(wala): use legalize(SourceVectNotLegalized, Legal_Mem) when support
     // for legalizing to mem is implemented.
     Variable *Slot = Func->makeVariable(Ty);
     Slot->setMustNotHaveReg();
     _movp(Slot, legalizeToReg(SourceVectNotLegalized));
 
     // Compute the location of the position to insert in memory.
     unsigned Offset = Index * typeWidthInBytes(InVectorElementTy);
-    typename Traits::X86OperandMem *Loc =
+    X86OperandMem *Loc =
         getMemoryOperandForStackSlot(InVectorElementTy, Slot, Offset);
     _store(legalizeToReg(ElementToInsertNotLegalized), Loc);
 
     Variable *T = makeReg(Ty);
     _movp(T, Slot);
     _movp(Inst->getDest(), T);
   }
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerIntrinsicCall(
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerIntrinsicCall(
     const InstIntrinsicCall *Instr) {
   switch (Intrinsics::IntrinsicID ID = Instr->getIntrinsicInfo().ID) {
   case Intrinsics::AtomicCmpxchg: {
     if (!Intrinsics::isMemoryOrderValid(
             ID, getConstantMemoryOrder(Instr->getArg(3)),
             getConstantMemoryOrder(Instr->getArg(4)))) {
       Func->setError("Unexpected memory ordering for AtomicCmpxchg");
       return;
     }
     Variable *DestPrev = Instr->getDest();
@@ skipping 59 matching lines @@
     }
     Variable *Dest = Instr->getDest();
     if (!Traits::Is64Bit) {
       if (auto *Dest64On32 = llvm::dyn_cast<Variable64On32>(Dest)) {
         // Follow what GCC does and use a movq instead of what lowerLoad()
         // normally does (split the load into two). Thus, this skips
         // load/arithmetic op folding. Load/arithmetic folding can't happen
         // anyway, since this is x86-32 and integer arithmetic only happens on
         // 32-bit quantities.
         Variable *T = makeReg(IceType_f64);
-        typename Traits::X86OperandMem *Addr =
-            formMemoryOperand(Instr->getArg(0), IceType_f64);
+        X86OperandMem *Addr = formMemoryOperand(Instr->getArg(0), IceType_f64);
         _movq(T, Addr);
         // Then cast the bits back out of the XMM register to the i64 Dest.
         auto *Cast = InstCast::create(Func, InstCast::Bitcast, Dest, T);
         lowerCast(Cast);
         // Make sure that the atomic load isn't elided when unused.
         Context.insert<InstFakeUse>(Dest64On32->getLo());
         Context.insert<InstFakeUse>(Dest64On32->getHi());
         return;
       }
     }
@@ skipping 29 matching lines @@
     Operand *Value = Instr->getArg(0);
     Operand *Ptr = Instr->getArg(1);
     if (!Traits::Is64Bit && Value->getType() == IceType_i64) {
       // Use a movq instead of what lowerStore() normally does (split the store
       // into two), following what GCC does. Cast the bits from int -> to an
       // xmm register first.
       Variable *T = makeReg(IceType_f64);
       auto *Cast = InstCast::create(Func, InstCast::Bitcast, T, Value);
       lowerCast(Cast);
       // Then store XMM w/ a movq.
-      typename Traits::X86OperandMem *Addr =
-          formMemoryOperand(Ptr, IceType_f64);
+      X86OperandMem *Addr = formMemoryOperand(Ptr, IceType_f64);
       _storeq(T, Addr);
       _mfence();
       return;
     }
     auto *Store = InstStore::create(Func, Value, Ptr);
     lowerStore(Store);
     _mfence();
     return;
   }
   case Intrinsics::Bswap: {
@@ skipping 123 matching lines @@
     return;
   }
   case Intrinsics::Fabs: {
     Operand *Src = legalize(Instr->getArg(0));
     Type Ty = Src->getType();
     Variable *Dest = Instr->getDest();
     Variable *T = makeVectorOfFabsMask(Ty);
     // The pand instruction operates on an m128 memory operand, so if Src is an
     // f32 or f64, we need to make sure it's in a register.
     if (isVectorType(Ty)) {
-      if (llvm::isa<typename Traits::X86OperandMem>(Src))
+      if (llvm::isa<X86OperandMem>(Src))
         Src = legalizeToReg(Src);
     } else {
       Src = legalizeToReg(Src);
     }
     _pand(T, Src);
     if (isVectorType(Ty))
       _movp(Dest, T);
     else
       _mov(Dest, T);
     return;
@@ skipping 12 matching lines @@
   case Intrinsics::Memmove: {
     lowerMemmove(Instr->getArg(0), Instr->getArg(1), Instr->getArg(2));
     return;
   }
   case Intrinsics::Memset: {
     lowerMemset(Instr->getArg(0), Instr->getArg(1), Instr->getArg(2));
     return;
   }
   case Intrinsics::NaClReadTP: {
     if (Ctx->getFlags().getUseSandboxing()) {
-      Operand *Src = dispatchToConcrete(&Machine::createNaClReadTPSrcOperand);
+      Operand *Src =
+          dispatchToConcrete(&ConcreteTarget::createNaClReadTPSrcOperand);
       Variable *Dest = Instr->getDest();
       Variable *T = nullptr;
       _mov(T, Src);
       _mov(Dest, T);
     } else {
       InstCall *Call = makeHelperCall(H_call_read_tp, Instr->getDest(), 0);
       lowerCall(Call);
     }
     return;
   }
@@ skipping 29 matching lines @@
   case Intrinsics::Trap:
     _ud2();
     return;
   case Intrinsics::UnknownIntrinsic:
     Func->setError("Should not be lowering UnknownIntrinsic");
     return;
   }
   return;
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerAtomicCmpxchg(Variable *DestPrev,
-                                                Operand *Ptr, Operand *Expected,
-                                                Operand *Desired) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerAtomicCmpxchg(Variable *DestPrev,
+                                                   Operand *Ptr,
+                                                   Operand *Expected,
+                                                   Operand *Desired) {
   Type Ty = Expected->getType();
   if (!Traits::Is64Bit && Ty == IceType_i64) {
     // Reserve the pre-colored registers first, before adding any more
     // infinite-weight variables from formMemoryOperand's legalization.
     Variable *T_edx = makeReg(IceType_i32, Traits::RegisterSet::Reg_edx);
     Variable *T_eax = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax);
     Variable *T_ecx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ecx);
     Variable *T_ebx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ebx);
     _mov(T_eax, loOperand(Expected));
     _mov(T_edx, hiOperand(Expected));
     _mov(T_ebx, loOperand(Desired));
     _mov(T_ecx, hiOperand(Desired));
-    typename Traits::X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
+    X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
     constexpr bool Locked = true;
     _cmpxchg8b(Addr, T_edx, T_eax, T_ecx, T_ebx, Locked);
     auto *DestLo = llvm::cast<Variable>(loOperand(DestPrev));
     auto *DestHi = llvm::cast<Variable>(hiOperand(DestPrev));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
   int32_t Eax;
   switch (Ty) {
   default:
     llvm::report_fatal_error("Bad type for cmpxchg");
   case IceType_i64:
     Eax = Traits::getRaxOrDie();
     break;
   case IceType_i32:
     Eax = Traits::RegisterSet::Reg_eax;
     break;
   case IceType_i16:
     Eax = Traits::RegisterSet::Reg_ax;
     break;
   case IceType_i8:
     Eax = Traits::RegisterSet::Reg_al;
     break;
   }
   Variable *T_eax = makeReg(Ty, Eax);
   _mov(T_eax, Expected);
-  typename Traits::X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
+  X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
   Variable *DesiredReg = legalizeToReg(Desired);
   constexpr bool Locked = true;
   _cmpxchg(Addr, T_eax, DesiredReg, Locked);
   _mov(DestPrev, T_eax);
 }
 
-template <class Machine>
-bool TargetX86Base<Machine>::tryOptimizedCmpxchgCmpBr(Variable *Dest,
-                                                      Operand *PtrToMem,
-                                                      Operand *Expected,
-                                                      Operand *Desired) {
+template <typename TraitsType>
+bool TargetX86Base<TraitsType>::tryOptimizedCmpxchgCmpBr(Variable *Dest,
+                                                         Operand *PtrToMem,
+                                                         Operand *Expected,
+                                                         Operand *Desired) {
   if (Ctx->getFlags().getOptLevel() == Opt_m1)
     return false;
   // Peek ahead a few instructions and see how Dest is used.
   // It's very common to have:
   //
   // %x = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* ptr, i32 %expected, ...)
   // [%y_phi = ...] // list of phi stores
   // %p = icmp eq i32 %x, %expected
   // br i1 %p, label %l1, label %l2
   //
@@ skipping 51 matching lines @@
         NextBr->setDeleted();
         Context.advanceNext();
         Context.advanceNext();
         return true;
       }
     }
   }
   return false;
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerAtomicRMW(Variable *Dest, uint32_t Operation,
-                                            Operand *Ptr, Operand *Val) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerAtomicRMW(Variable *Dest,
+                                               uint32_t Operation, Operand *Ptr,
+                                               Operand *Val) {
   bool NeedsCmpxchg = false;
   LowerBinOp Op_Lo = nullptr;
   LowerBinOp Op_Hi = nullptr;
   switch (Operation) {
   default:
     Func->setError("Unknown AtomicRMW operation");
     return;
   case Intrinsics::AtomicAdd: {
     if (!Traits::Is64Bit && Dest->getType() == IceType_i64) {
       // All the fall-through paths must set this to true, but use this
       // for asserting.
       NeedsCmpxchg = true;
-      Op_Lo = &TargetX86Base<Machine>::_add;
-      Op_Hi = &TargetX86Base<Machine>::_adc;
+      Op_Lo = &TargetX86Base<TraitsType>::_add;
+      Op_Hi = &TargetX86Base<TraitsType>::_adc;
       break;
     }
-    typename Traits::X86OperandMem *Addr =
-        formMemoryOperand(Ptr, Dest->getType());
+    X86OperandMem *Addr = formMemoryOperand(Ptr, Dest->getType());
     constexpr bool Locked = true;
     Variable *T = nullptr;
     _mov(T, Val);
     _xadd(Addr, T, Locked);
     _mov(Dest, T);
     return;
   }
   case Intrinsics::AtomicSub: {
     if (!Traits::Is64Bit && Dest->getType() == IceType_i64) {
       NeedsCmpxchg = true;
-      Op_Lo = &TargetX86Base<Machine>::_sub;
-      Op_Hi = &TargetX86Base<Machine>::_sbb;
+      Op_Lo = &TargetX86Base<TraitsType>::_sub;
+      Op_Hi = &TargetX86Base<TraitsType>::_sbb;
       break;
     }
-    typename Traits::X86OperandMem *Addr =
-        formMemoryOperand(Ptr, Dest->getType());
+    X86OperandMem *Addr = formMemoryOperand(Ptr, Dest->getType());
     constexpr bool Locked = true;
     Variable *T = nullptr;
     _mov(T, Val);
     _neg(T);
     _xadd(Addr, T, Locked);
     _mov(Dest, T);
     return;
   }
   case Intrinsics::AtomicOr:
     // TODO(jvoung): If Dest is null or dead, then some of these
     // operations do not need an "exchange", but just a locked op.
     // That appears to be "worth" it for sub, or, and, and xor.
     // xadd is probably fine vs lock add for add, and xchg is fine
     // vs an atomic store.
     NeedsCmpxchg = true;
-    Op_Lo = &TargetX86Base<Machine>::_or;
-    Op_Hi = &TargetX86Base<Machine>::_or;
+    Op_Lo = &TargetX86Base<TraitsType>::_or;
+    Op_Hi = &TargetX86Base<TraitsType>::_or;
     break;
   case Intrinsics::AtomicAnd:
     NeedsCmpxchg = true;
-    Op_Lo = &TargetX86Base<Machine>::_and;
-    Op_Hi = &TargetX86Base<Machine>::_and;
+    Op_Lo = &TargetX86Base<TraitsType>::_and;
+    Op_Hi = &TargetX86Base<TraitsType>::_and;
     break;
   case Intrinsics::AtomicXor:
     NeedsCmpxchg = true;
-    Op_Lo = &TargetX86Base<Machine>::_xor;
-    Op_Hi = &TargetX86Base<Machine>::_xor;
+    Op_Lo = &TargetX86Base<TraitsType>::_xor;
+    Op_Hi = &TargetX86Base<TraitsType>::_xor;
     break;
   case Intrinsics::AtomicExchange:
     if (!Traits::Is64Bit && Dest->getType() == IceType_i64) {
       NeedsCmpxchg = true;
       // NeedsCmpxchg, but no real Op_Lo/Op_Hi need to be done. The values
       // just need to be moved to the ecx and ebx registers.
       Op_Lo = nullptr;
       Op_Hi = nullptr;
       break;
     }
-    typename Traits::X86OperandMem *Addr =
-        formMemoryOperand(Ptr, Dest->getType());
+    X86OperandMem *Addr = formMemoryOperand(Ptr, Dest->getType());
     Variable *T = nullptr;
     _mov(T, Val);
     _xchg(Addr, T);
     _mov(Dest, T);
     return;
   }
   // Otherwise, we need a cmpxchg loop.
   (void)NeedsCmpxchg;
   assert(NeedsCmpxchg);
   expandAtomicRMWAsCmpxchg(Op_Lo, Op_Hi, Dest, Ptr, Val);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::expandAtomicRMWAsCmpxchg(LowerBinOp Op_Lo,
-                                                      LowerBinOp Op_Hi,
-                                                      Variable *Dest,
-                                                      Operand *Ptr,
-                                                      Operand *Val) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::expandAtomicRMWAsCmpxchg(LowerBinOp Op_Lo,
+                                                         LowerBinOp Op_Hi,
+                                                         Variable *Dest,
+                                                         Operand *Ptr,
+                                                         Operand *Val) {
   // Expand a more complex RMW operation as a cmpxchg loop:
   // For 64-bit:
   //   mov     eax, [ptr]
   //   mov     edx, [ptr + 4]
   // .LABEL:
   //   mov     ebx, eax
   //   <Op_Lo> ebx, <desired_adj_lo>
   //   mov     ecx, edx
   //   <Op_Hi> ecx, <desired_adj_hi>
   //   lock cmpxchg8b [ptr]
   //   jne     .LABEL
   //   mov     <dest_lo>, eax
   //   mov     <dest_lo>, edx
   //
   // For 32-bit:
   //   mov     eax, [ptr]
   // .LABEL:
   //   mov     <reg>, eax
   //   op      <reg>, [desired_adj]
   //   lock cmpxchg [ptr], <reg>
   //   jne     .LABEL
   //   mov     <dest>, eax
   //
   // If Op_{Lo,Hi} are nullptr, then just copy the value.
   Val = legalize(Val);
   Type Ty = Val->getType();
   if (!Traits::Is64Bit && Ty == IceType_i64) {
     Variable *T_edx = makeReg(IceType_i32, Traits::RegisterSet::Reg_edx);
     Variable *T_eax = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax);
-    typename Traits::X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
+    X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
     _mov(T_eax, loOperand(Addr));
     _mov(T_edx, hiOperand(Addr));
     Variable *T_ecx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ecx);
     Variable *T_ebx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ebx);
-    typename Traits::Insts::Label *Label =
-        Traits::Insts::Label::create(Func, this);
+    InstX86Label *Label = InstX86Label::create(Func, this);
     const bool IsXchg8b = Op_Lo == nullptr && Op_Hi == nullptr;
     if (!IsXchg8b) {
       Context.insert(Label);
       _mov(T_ebx, T_eax);
       (this->*Op_Lo)(T_ebx, loOperand(Val));
       _mov(T_ecx, T_edx);
       (this->*Op_Hi)(T_ecx, hiOperand(Val));
     } else {
       // This is for xchg, which doesn't need an actual Op_Lo/Op_Hi.
       // It just needs the Val loaded into ebx and ecx.
@@ skipping 21 matching lines @@
     }
     // The address base (if any) is also reused in the loop.
     if (Variable *Base = Addr->getBase())
       Context.insert<InstFakeUse>(Base);
     auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
     auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
-  typename Traits::X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
+  X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
   int32_t Eax;
   switch (Ty) {
   default:
     llvm::report_fatal_error("Bad type for atomicRMW");
   case IceType_i64:
     Eax = Traits::getRaxOrDie();
     break;
   case IceType_i32:
     Eax = Traits::RegisterSet::Reg_eax;
     break;
   case IceType_i16:
     Eax = Traits::RegisterSet::Reg_ax;
     break;
   case IceType_i8:
     Eax = Traits::RegisterSet::Reg_al;
     break;
   }
   Variable *T_eax = makeReg(Ty, Eax);
   _mov(T_eax, Addr);
-  auto *Label = Context.insert<typename Traits::Insts::Label>(this);
+  auto *Label = Context.insert<InstX86Label>(this);
   // We want to pick a different register for T than Eax, so don't use
   // _mov(T == nullptr, T_eax).
   Variable *T = makeReg(Ty);
   _mov(T, T_eax);
   (this->*Op_Lo)(T, Val);
   constexpr bool Locked = true;
   _cmpxchg(Addr, T_eax, T, Locked);
   _br(Traits::Cond::Br_ne, Label);
   // If Val is a variable, model the extended live range of Val through
   // the end of the loop, since it will be re-used by the loop.
   if (auto *ValVar = llvm::dyn_cast<Variable>(Val)) {
     Context.insert<InstFakeUse>(ValVar);
   }
   // The address base (if any) is also reused in the loop.
   if (Variable *Base = Addr->getBase())
     Context.insert<InstFakeUse>(Base);
   _mov(Dest, T_eax);
 }
 
 /// Lowers count {trailing, leading} zeros intrinsic.
 ///
 /// We could do constant folding here, but that should have
 /// been done by the front-end/middle-end optimizations.
-template <class Machine>
-void TargetX86Base<Machine>::lowerCountZeros(bool Cttz, Type Ty, Variable *Dest,
-                                             Operand *FirstVal,
-                                             Operand *SecondVal) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerCountZeros(bool Cttz, Type Ty,
+                                                Variable *Dest,
+                                                Operand *FirstVal,
+                                                Operand *SecondVal) {
   // TODO(jvoung): Determine if the user CPU supports LZCNT (BMI).
   // Then the instructions will handle the Val == 0 case much more simply
   // and won't require conversion from bit position to number of zeros.
   //
   // Otherwise:
   //   bsr IF_NOT_ZERO, Val
   //   mov T_DEST, 63
   //   cmovne T_DEST, IF_NOT_ZERO
   //   xor T_DEST, 31
   //   mov DEST, T_DEST
@@ skipping 51 matching lines @@
   } else {
     _bsr(T_Dest2, SecondVar);
     _xor(T_Dest2, _31);
   }
   _test(SecondVar, SecondVar);
   _cmov(T_Dest2, T_Dest, Traits::Cond::Br_e);
   _mov(DestLo, T_Dest2);
   _mov(DestHi, Ctx->getConstantZero(IceType_i32));
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::typedLoad(Type Ty, Variable *Dest, Variable *Base,
-                                       Constant *Offset) {
-  auto *Mem = Traits::X86OperandMem::create(Func, Ty, Base, Offset);
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::typedLoad(Type Ty, Variable *Dest,
+                                          Variable *Base, Constant *Offset) {
+  auto *Mem = X86OperandMem::create(Func, Ty, Base, Offset);
 
   if (isVectorType(Ty))
     _movp(Dest, Mem);
   else if (Ty == IceType_f64)
     _movq(Dest, Mem);
   else
     _mov(Dest, Mem);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::typedStore(Type Ty, Variable *Value,
-                                        Variable *Base, Constant *Offset) {
-  auto *Mem = Traits::X86OperandMem::create(Func, Ty, Base, Offset);
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::typedStore(Type Ty, Variable *Value,
+                                           Variable *Base, Constant *Offset) {
+  auto *Mem = X86OperandMem::create(Func, Ty, Base, Offset);
 
   if (isVectorType(Ty))
     _storep(Value, Mem);
   else if (Ty == IceType_f64)
     _storeq(Value, Mem);
   else
     _store(Value, Mem);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::copyMemory(Type Ty, Variable *Dest, Variable *Src,
-                                        int32_t OffsetAmt) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::copyMemory(Type Ty, Variable *Dest,
+                                           Variable *Src, int32_t OffsetAmt) {
   Constant *Offset = OffsetAmt ? Ctx->getConstantInt32(OffsetAmt) : nullptr;
   // TODO(ascull): this or add nullptr test to _movp, _movq
   Variable *Data = makeReg(Ty);
 
   typedLoad(Ty, Data, Src, Offset);
   typedStore(Ty, Data, Dest, Offset);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerMemcpy(Operand *Dest, Operand *Src,
-                                         Operand *Count) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerMemcpy(Operand *Dest, Operand *Src,
+                                            Operand *Count) {
   // There is a load and store for each chunk in the unroll
   constexpr uint32_t BytesPerStorep = 16;
 
   // Check if the operands are constants
   const auto *CountConst = llvm::dyn_cast<const ConstantInteger32>(Count);
   const bool IsCountConst = CountConst != nullptr;
   const uint32_t CountValue = IsCountConst ? CountConst->getValue() : 0;
 
   if (shouldOptimizeMemIntrins() && IsCountConst &&
       CountValue <= BytesPerStorep * Traits::MEMCPY_UNROLL_LIMIT) {
@@ skipping 31 matching lines @@
   }
 
   // Fall back on a function call
   InstCall *Call = makeHelperCall(H_call_memcpy, nullptr, 3);
   Call->addArg(Dest);
   Call->addArg(Src);
   Call->addArg(Count);
   lowerCall(Call);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerMemmove(Operand *Dest, Operand *Src,
-                                          Operand *Count) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerMemmove(Operand *Dest, Operand *Src,
+                                             Operand *Count) {
   // There is a load and store for each chunk in the unroll
   constexpr uint32_t BytesPerStorep = 16;
 
   // Check if the operands are constants
   const auto *CountConst = llvm::dyn_cast<const ConstantInteger32>(Count);
   const bool IsCountConst = CountConst != nullptr;
   const uint32_t CountValue = IsCountConst ? CountConst->getValue() : 0;
 
   if (shouldOptimizeMemIntrins() && IsCountConst &&
       CountValue <= BytesPerStorep * Traits::MEMMOVE_UNROLL_LIMIT) {
@@ skipping 49 matching lines @@
   }
 
   // Fall back on a function call
   InstCall *Call = makeHelperCall(H_call_memmove, nullptr, 3);
   Call->addArg(Dest);
   Call->addArg(Src);
   Call->addArg(Count);
   lowerCall(Call);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerMemset(Operand *Dest, Operand *Val,
-                                         Operand *Count) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerMemset(Operand *Dest, Operand *Val,
+                                            Operand *Count) {
   constexpr uint32_t BytesPerStorep = 16;
   constexpr uint32_t BytesPerStoreq = 8;
   constexpr uint32_t BytesPerStorei32 = 4;
   assert(Val->getType() == IceType_i8);
 
   // Check if the operands are constants
   const auto *CountConst = llvm::dyn_cast<const ConstantInteger32>(Count);
   const auto *ValConst = llvm::dyn_cast<const ConstantInteger32>(Val);
   const bool IsCountConst = CountConst != nullptr;
   const bool IsValConst = ValConst != nullptr;
@@ skipping 12 matching lines @@
     Variable *VecReg = nullptr;
     const uint32_t SpreadValue =
         (ValValue << 24) | (ValValue << 16) | (ValValue << 8) | ValValue;
 
     auto lowerSet = [this, &Base, SpreadValue, &VecReg](Type Ty,
                                                         uint32_t OffsetAmt) {
       assert(Base != nullptr);
       Constant *Offset = OffsetAmt ? Ctx->getConstantInt32(OffsetAmt) : nullptr;
 
       // TODO(ascull): is 64-bit better with vector or scalar movq?
-      auto *Mem = Traits::X86OperandMem::create(Func, Ty, Base, Offset);
+      auto *Mem = X86OperandMem::create(Func, Ty, Base, Offset);
       if (isVectorType(Ty)) {
         assert(VecReg != nullptr);
         _storep(VecReg, Mem);
       } else if (Ty == IceType_f64) {
         assert(VecReg != nullptr);
         _storeq(VecReg, Mem);
       } else {
         assert(Ty != IceType_i64);
         _store(Ctx->getConstantInt(Ty, SpreadValue), Mem);
       }
@@ skipping 53 matching lines @@
     lowerCast(InstCast::create(Func, InstCast::Zext, ValExtVar, Val));
     ValExt = ValExtVar;
   }
   InstCall *Call = makeHelperCall(H_call_memset, nullptr, 3);
   Call->addArg(Dest);
   Call->addArg(ValExt);
   Call->addArg(Count);
   lowerCall(Call);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerIndirectJump(Variable *JumpTarget) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerIndirectJump(Variable *JumpTarget) {
   const bool NeedSandboxing = Ctx->getFlags().getUseSandboxing();
   if (Traits::Is64Bit) {
     Variable *T = makeReg(IceType_i64);
     _movzx(T, JumpTarget);
     JumpTarget = T;
   }
   if (NeedSandboxing) {
     _bundle_lock();
     const SizeT BundleSize =
         1 << Func->getAssembler<>()->getBundleAlignLog2Bytes();
@@ skipping 376 matching lines @@
 /// For the purpose of mocking the bounds check, we'll do something like this:
 ///
 ///   cmp reg, 0
 ///   je label
 ///   cmp reg, 1
 ///   je label
 ///   label:
 ///
 /// Also note that we don't need to add a bounds check to a dereference of a
 /// simple global variable address.
-template <class Machine>
-void TargetX86Base<Machine>::doMockBoundsCheck(Operand *Opnd) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::doMockBoundsCheck(Operand *Opnd) {
   if (!Ctx->getFlags().getMockBoundsCheck())
     return;
-  if (auto *Mem = llvm::dyn_cast<typename Traits::X86OperandMem>(Opnd)) {
+  if (auto *Mem = llvm::dyn_cast<X86OperandMem>(Opnd)) {
     if (Mem->getIndex()) {
       llvm::report_fatal_error("doMockBoundsCheck: Opnd contains index reg");
     }
     Opnd = Mem->getBase();
   }
   // At this point Opnd could be nullptr, or Variable, or Constant, or perhaps
   // something else.  We only care if it is Variable.
   auto *Var = llvm::dyn_cast_or_null<Variable>(Opnd);
   if (Var == nullptr)
     return;
   // We use lowerStore() to copy out-args onto the stack.  This creates a memory
   // operand with the stack pointer as the base register.  Don't do bounds
   // checks on that.
   if (Var->getRegNum() == static_cast<int32_t>(getStackReg()))
     return;
 
-  auto *Label = Traits::Insts::Label::create(Func, this);
+  auto *Label = InstX86Label::create(Func, this);
   _cmp(Opnd, Ctx->getConstantZero(IceType_i32));
   _br(Traits::Cond::Br_e, Label);
   _cmp(Opnd, Ctx->getConstantInt32(1));
   _br(Traits::Cond::Br_e, Label);
   Context.insert(Label);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerLoad(const InstLoad *Load) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerLoad(const InstLoad *Load) {
   // A Load instruction can be treated the same as an Assign instruction, after
-  // the source operand is transformed into an Traits::X86OperandMem operand.
+  // the source operand is transformed into an X86OperandMem operand.
   // Note that the address mode optimization already creates an
-  // Traits::X86OperandMem operand, so it doesn't need another level of
+  // X86OperandMem operand, so it doesn't need another level of
   // transformation.
   Variable *DestLoad = Load->getDest();
   Type Ty = DestLoad->getType();
   Operand *Src0 = formMemoryOperand(Load->getSourceAddress(), Ty);
   doMockBoundsCheck(Src0);
   auto *Assign = InstAssign::create(Func, DestLoad, Src0);
   lowerAssign(Assign);
 }
 
-template <class Machine> void TargetX86Base<Machine>::doAddressOptLoad() {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::doAddressOptLoad() {
   Inst *Inst = Context.getCur();
   Variable *Dest = Inst->getDest();
   Operand *Addr = Inst->getSrc(0);
   Variable *Index = nullptr;
   ConstantRelocatable *Relocatable = nullptr;
   uint16_t Shift = 0;
   int32_t Offset = 0;
   // Vanilla ICE load instructions should not use the segment registers, and
   // computeAddressOpt only works at the level of Variables and Constants, not
-  // other Traits::X86OperandMem, so there should be no mention of segment
+  // other X86OperandMem, so there should be no mention of segment
   // registers there either.
-  const typename Traits::X86OperandMem::SegmentRegisters SegmentReg =
-      Traits::X86OperandMem::DefaultSegment;
+  const SegmentRegisters SegmentReg = X86OperandMem::DefaultSegment;
   auto *Base = llvm::dyn_cast<Variable>(Addr);
   if (computeAddressOpt(Func, Inst, Relocatable, Offset, Base, Index, Shift)) {
     Inst->setDeleted();
     Constant *OffsetOp = nullptr;
     if (Relocatable == nullptr) {
       OffsetOp = Ctx->getConstantInt32(Offset);
     } else {
       OffsetOp = Ctx->getConstantSym(Relocatable->getOffset() + Offset,
                                      Relocatable->getName(),
                                      Relocatable->getSuppressMangling());
     }
-    Addr = Traits::X86OperandMem::create(Func, Dest->getType(), Base, OffsetOp,
-                                         Index, Shift, SegmentReg);
+    Addr = X86OperandMem::create(Func, Dest->getType(), Base, OffsetOp, Index,
+                                 Shift, SegmentReg);
     Context.insert<InstLoad>(Dest, Addr);
   }
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::randomlyInsertNop(float Probability,
-                                               RandomNumberGenerator &RNG) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::randomlyInsertNop(float Probability,
+                                                  RandomNumberGenerator &RNG) {
   RandomNumberGeneratorWrapper RNGW(RNG);
   if (RNGW.getTrueWithProbability(Probability)) {
     _nop(RNGW(Traits::X86_NUM_NOP_VARIANTS));
   }
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerPhi(const InstPhi * /*Inst*/) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerPhi(const InstPhi * /*Inst*/) {
   Func->setError("Phi found in regular instruction list");
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerSelect(const InstSelect *Select) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerSelect(const InstSelect *Select) {
   Variable *Dest = Select->getDest();
 
   if (isVectorType(Dest->getType())) {
     lowerSelectVector(Select);
     return;
   }
 
   Operand *Condition = Select->getCondition();
   // Handle folding opportunities.
   if (const Inst *Producer = FoldingInfo.getProducerFor(Condition)) {
@@ skipping 11 matching lines @@
       return;
     }
     }
   }
 
   Operand *CmpResult = legalize(Condition, Legal_Reg | Legal_Mem);
   Operand *Zero = Ctx->getConstantZero(IceType_i32);
   _cmp(CmpResult, Zero);
   Operand *SrcT = Select->getTrueOperand();
   Operand *SrcF = Select->getFalseOperand();
-  const typename Traits::Cond::BrCond Cond = Traits::Cond::Br_ne;
+  const BrCond Cond = Traits::Cond::Br_ne;
   lowerSelectMove(Dest, Cond, SrcT, SrcF);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerSelectMove(Variable *Dest,
-                                             typename Traits::Cond::BrCond Cond,
-                                             Operand *SrcT, Operand *SrcF) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerSelectMove(Variable *Dest, BrCond Cond,
+                                                Operand *SrcT, Operand *SrcF) {
   Type DestTy = Dest->getType();
   if (typeWidthInBytes(DestTy) == 1 || isFloatingType(DestTy)) {
     // The cmov instruction doesn't allow 8-bit or FP operands, so we need
     // explicit control flow.
     // d=cmp e,f; a=d?b:c ==> cmp e,f; a=b; jne L1; a=c; L1:
-    auto *Label = Traits::Insts::Label::create(Func, this);
+    auto *Label = InstX86Label::create(Func, this);
     SrcT = legalize(SrcT, Legal_Reg | Legal_Imm);
     _mov(Dest, SrcT);
     _br(Cond, Label);
     SrcF = legalize(SrcF, Legal_Reg | Legal_Imm);
     _redefined(_mov(Dest, SrcF));
     Context.insert(Label);
     return;
   }
   // mov t, SrcF; cmov_cond t, SrcT; mov dest, t
   // But if SrcT is immediate, we might be able to do better, as the cmov
   // instruction doesn't allow an immediate operand:
   // mov t, SrcT; cmov_!cond t, SrcF; mov dest, t
   if (llvm::isa<Constant>(SrcT) && !llvm::isa<Constant>(SrcF)) {
     std::swap(SrcT, SrcF);
-    Cond = InstX86Base<Machine>::getOppositeCondition(Cond);
+    Cond = InstImpl<TraitsType>::InstX86Base::getOppositeCondition(Cond);
   }
   if (!Traits::Is64Bit && DestTy == IceType_i64) {
     SrcT = legalizeUndef(SrcT);
     SrcF = legalizeUndef(SrcF);
     // Set the low portion.
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
     lowerSelectIntMove(DestLo, Cond, loOperand(SrcT), loOperand(SrcF));
     // Set the high portion.
     Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     lowerSelectIntMove(DestHi, Cond, hiOperand(SrcT), hiOperand(SrcF));
     return;
   }
 
   assert(DestTy == IceType_i16 || DestTy == IceType_i32 ||
          (Traits::Is64Bit && DestTy == IceType_i64));
   lowerSelectIntMove(Dest, Cond, SrcT, SrcF);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerSelectIntMove(
-    Variable *Dest, typename Traits::Cond::BrCond Cond, Operand *SrcT,
-    Operand *SrcF) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerSelectIntMove(Variable *Dest, BrCond Cond,
+                                                   Operand *SrcT,
+                                                   Operand *SrcF) {
   Variable *T = nullptr;
   SrcF = legalize(SrcF);
   _mov(T, SrcF);
   SrcT = legalize(SrcT, Legal_Reg | Legal_Mem);
   _cmov(T, SrcT, Cond);
   _mov(Dest, T);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerMove(Variable *Dest, Operand *Src,
-                                       bool IsRedefinition) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerMove(Variable *Dest, Operand *Src,
+                                          bool IsRedefinition) {
   assert(Dest->getType() == Src->getType());
   assert(!Dest->isRematerializable());
   if (!Traits::Is64Bit && Dest->getType() == IceType_i64) {
     Src = legalize(Src);
     Operand *SrcLo = loOperand(Src);
     Operand *SrcHi = hiOperand(Src);
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     Variable *T_Lo = nullptr, *T_Hi = nullptr;
     _mov(T_Lo, SrcLo);
@@ skipping 13 matching lines @@
       SrcLegal = legalize(Src, Legal_Reg | Legal_Imm);
     }
     if (isVectorType(Dest->getType())) {
       _redefined(_movp(Dest, SrcLegal), IsRedefinition);
     } else {
       _redefined(_mov(Dest, SrcLegal), IsRedefinition);
     }
   }
 }
 
-template <class Machine>
-bool TargetX86Base<Machine>::lowerOptimizeFcmpSelect(const InstFcmp *Fcmp,
-                                                     const InstSelect *Select) {
+template <typename TraitsType>
+bool TargetX86Base<TraitsType>::lowerOptimizeFcmpSelect(
+    const InstFcmp *Fcmp, const InstSelect *Select) {
   Operand *CmpSrc0 = Fcmp->getSrc(0);
   Operand *CmpSrc1 = Fcmp->getSrc(1);
   Operand *SelectSrcT = Select->getTrueOperand();
   Operand *SelectSrcF = Select->getFalseOperand();
 
   if (CmpSrc0->getType() != SelectSrcT->getType())
     return false;
 
   // TODO(sehr, stichnot): fcmp/select patterns (e,g., minsd/maxss) go here.
   InstFcmp::FCond Condition = Fcmp->getCondition();
   switch (Condition) {
   default:
     return false;
   case InstFcmp::True:
   case InstFcmp::False:
   case InstFcmp::Ogt:
   case InstFcmp::Olt:
     (void)CmpSrc0;
     (void)CmpSrc1;
     (void)SelectSrcT;
     (void)SelectSrcF;
     break;
   }
   return false;
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerIcmp(const InstIcmp *Icmp) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerIcmp(const InstIcmp *Icmp) {
   Variable *Dest = Icmp->getDest();
   if (isVectorType(Dest->getType())) {
     lowerIcmpVector(Icmp);
   } else {
     constexpr Inst *Consumer = nullptr;
     lowerIcmpAndConsumer(Icmp, Consumer);
   }
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerSelectVector(const InstSelect *Inst) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerSelectVector(const InstSelect *Inst) {
   Variable *Dest = Inst->getDest();
   Type DestTy = Dest->getType();
   Operand *SrcT = Inst->getTrueOperand();
   Operand *SrcF = Inst->getFalseOperand();
   Operand *Condition = Inst->getCondition();
 
   if (!isVectorType(DestTy))
     llvm::report_fatal_error("Expected a vector select");
 
   Type SrcTy = SrcT->getType();
@@ skipping 46 matching lines @@
   }
   _movp(T2, T);
   _pand(T, SrcTRM);
   _pandn(T2, SrcFRM);
   _por(T, T2);
   _movp(Dest, T);
 
   return;
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerStore(const InstStore *Inst) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerStore(const InstStore *Inst) {
   Operand *Value = Inst->getData();
   Operand *Addr = Inst->getAddr();
-  typename Traits::X86OperandMem *NewAddr =
-      formMemoryOperand(Addr, Value->getType());
+  X86OperandMem *NewAddr = formMemoryOperand(Addr, Value->getType());
   doMockBoundsCheck(NewAddr);
   Type Ty = NewAddr->getType();
 
   if (!Traits::Is64Bit && Ty == IceType_i64) {
     Value = legalizeUndef(Value);
     Operand *ValueHi = legalize(hiOperand(Value), Legal_Reg | Legal_Imm);
     Operand *ValueLo = legalize(loOperand(Value), Legal_Reg | Legal_Imm);
-    _store(ValueHi,
-           llvm::cast<typename Traits::X86OperandMem>(hiOperand(NewAddr)));
-    _store(ValueLo,
-           llvm::cast<typename Traits::X86OperandMem>(loOperand(NewAddr)));
+    _store(ValueHi, llvm::cast<X86OperandMem>(hiOperand(NewAddr)));
+    _store(ValueLo, llvm::cast<X86OperandMem>(loOperand(NewAddr)));
   } else if (isVectorType(Ty)) {
     _storep(legalizeToReg(Value), NewAddr);
   } else {
     Value = legalize(Value, Legal_Reg | Legal_Imm);
     _store(Value, NewAddr);
   }
 }
 
-template <class Machine> void TargetX86Base<Machine>::doAddressOptStore() {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::doAddressOptStore() {
   auto *Inst = llvm::cast<InstStore>(Context.getCur());
   Operand *Data = Inst->getData();
   Operand *Addr = Inst->getAddr();
   Variable *Index = nullptr;
   ConstantRelocatable *Relocatable = nullptr;
   uint16_t Shift = 0;
   int32_t Offset = 0;
   auto *Base = llvm::dyn_cast<Variable>(Addr);
   // Vanilla ICE store instructions should not use the segment registers, and
   // computeAddressOpt only works at the level of Variables and Constants, not
-  // other Traits::X86OperandMem, so there should be no mention of segment
+  // other X86OperandMem, so there should be no mention of segment
   // registers there either.
-  const typename Traits::X86OperandMem::SegmentRegisters SegmentReg =
-      Traits::X86OperandMem::DefaultSegment;
+  const SegmentRegisters SegmentReg = X86OperandMem::DefaultSegment;
   if (computeAddressOpt(Func, Inst, Relocatable, Offset, Base, Index, Shift)) {
     Inst->setDeleted();
     Constant *OffsetOp = nullptr;
     if (Relocatable == nullptr) {
       OffsetOp = Ctx->getConstantInt32(Offset);
     } else {
       OffsetOp = Ctx->getConstantSym(Relocatable->getOffset() + Offset,
                                      Relocatable->getName(),
                                      Relocatable->getSuppressMangling());
     }
-    Addr = Traits::X86OperandMem::create(Func, Data->getType(), Base, OffsetOp,
-                                         Index, Shift, SegmentReg);
+    Addr = X86OperandMem::create(Func, Data->getType(), Base, OffsetOp, Index,
+                                 Shift, SegmentReg);
     auto *NewStore = Context.insert<InstStore>(Data, Addr);
     if (Inst->getDest())
       NewStore->setRmwBeacon(Inst->getRmwBeacon());
   }
 }
 
-template <class Machine>
-Operand *TargetX86Base<Machine>::lowerCmpRange(Operand *Comparison,
-                                               uint64_t Min, uint64_t Max) {
+template <typename TraitsType>
+Operand *TargetX86Base<TraitsType>::lowerCmpRange(Operand *Comparison,
+                                                  uint64_t Min, uint64_t Max) {
   // TODO(ascull): 64-bit should not reach here but only because it is not
   // implemented yet. This should be able to handle the 64-bit case.
   assert(Traits::Is64Bit || Comparison->getType() != IceType_i64);
   // Subtracting 0 is a nop so don't do it
   if (Min != 0) {
     // Avoid clobbering the comparison by copying it
     Variable *T = nullptr;
     _mov(T, Comparison);
     _sub(T, Ctx->getConstantInt32(Min));
     Comparison = T;
   }
 
   _cmp(Comparison, Ctx->getConstantInt32(Max - Min));
 
   return Comparison;
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerCaseCluster(const CaseCluster &Case,
-                                              Operand *Comparison, bool DoneCmp,
-                                              CfgNode *DefaultTarget) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerCaseCluster(const CaseCluster &Case,
+                                                 Operand *Comparison,
+                                                 bool DoneCmp,
+                                                 CfgNode *DefaultTarget) {
   switch (Case.getKind()) {
   case CaseCluster::JumpTable: {
-    typename Traits::Insts::Label *SkipJumpTable;
+    InstX86Label *SkipJumpTable;
 
     Operand *RangeIndex =
         lowerCmpRange(Comparison, Case.getLow(), Case.getHigh());
     if (DefaultTarget == nullptr) {
       // Skip over jump table logic if comparison not in range and no default
-      SkipJumpTable = Traits::Insts::Label::create(Func, this);
+      SkipJumpTable = InstX86Label::create(Func, this);
       _br(Traits::Cond::Br_a, SkipJumpTable);
     } else {
       _br(Traits::Cond::Br_a, DefaultTarget);
     }
 
     InstJumpTable *JumpTable = Case.getJumpTable();
     Context.insert(JumpTable);
 
     // Make sure the index is a register of the same width as the base
     Variable *Index;
     if (RangeIndex->getType() != getPointerType()) {
       Index = makeReg(getPointerType());
       _movzx(Index, RangeIndex);
     } else {
       Index = legalizeToReg(RangeIndex);
     }
 
     constexpr RelocOffsetT RelocOffset = 0;
     constexpr bool SuppressMangling = true;
     IceString MangledName = Ctx->mangleName(Func->getFunctionName());
     Constant *Base = Ctx->getConstantSym(
         RelocOffset, InstJumpTable::makeName(MangledName, JumpTable->getId()),
         SuppressMangling);
     Constant *Offset = nullptr;
     uint16_t Shift = typeWidthInBytesLog2(getPointerType());
     // TODO(ascull): remove need for legalize by allowing null base in memop
-    auto *TargetInMemory = Traits::X86OperandMem::create(
+    auto *TargetInMemory = X86OperandMem::create(
         Func, getPointerType(), legalizeToReg(Base), Offset, Index, Shift);
     Variable *Target = nullptr;
     _mov(Target, TargetInMemory);
     lowerIndirectJump(Target);
 
     if (DefaultTarget == nullptr)
       Context.insert(SkipJumpTable);
     return;
   }
   case CaseCluster::Range: {
@@ skipping 15 matching lines @@
       lowerCmpRange(Comparison, Case.getLow(), Case.getHigh());
       _br(Traits::Cond::Br_be, Case.getTarget());
     }
     if (DefaultTarget != nullptr)
       _br(DefaultTarget);
     return;
   }
   }
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerSwitch(const InstSwitch *Inst) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerSwitch(const InstSwitch *Inst) {
   // Group cases together and navigate through them with a binary search
   CaseClusterArray CaseClusters = CaseCluster::clusterizeSwitch(Func, Inst);
   Operand *Src0 = Inst->getComparison();
   CfgNode *DefaultTarget = Inst->getLabelDefault();
 
   assert(CaseClusters.size() != 0); // Should always be at least one
 
   if (!Traits::Is64Bit && Src0->getType() == IceType_i64) {
     Src0 = legalize(Src0); // get Base/Index into physical registers
     Operand *Src0Lo = loOperand(Src0);
     Operand *Src0Hi = hiOperand(Src0);
     if (CaseClusters.back().getHigh() > UINT32_MAX) {
       // TODO(ascull): handle 64-bit case properly (currently naive version)
       // This might be handled by a higher level lowering of switches.
       SizeT NumCases = Inst->getNumCases();
       if (NumCases >= 2) {
         Src0Lo = legalizeToReg(Src0Lo);
         Src0Hi = legalizeToReg(Src0Hi);
       } else {
         Src0Lo = legalize(Src0Lo, Legal_Reg | Legal_Mem);
         Src0Hi = legalize(Src0Hi, Legal_Reg | Legal_Mem);
       }
       for (SizeT I = 0; I < NumCases; ++I) {
         Constant *ValueLo = Ctx->getConstantInt32(Inst->getValue(I));
         Constant *ValueHi = Ctx->getConstantInt32(Inst->getValue(I) >> 32);
-        typename Traits::Insts::Label *Label =
-            Traits::Insts::Label::create(Func, this);
+        InstX86Label *Label = InstX86Label::create(Func, this);
         _cmp(Src0Lo, ValueLo);
         _br(Traits::Cond::Br_ne, Label);
         _cmp(Src0Hi, ValueHi);
         _br(Traits::Cond::Br_e, Inst->getLabel(I));
         Context.insert(Label);
       }
       _br(Inst->getLabelDefault());
       return;
     } else {
       // All the values are 32-bit so just check the operand is too and then
@@ skipping 14 matching lines @@
     constexpr bool DoneCmp = false;
     lowerCaseCluster(CaseClusters.front(), Src0, DoneCmp, DefaultTarget);
     return;
   }
 
   // Going to be using multiple times so get it in a register early
   Variable *Comparison = legalizeToReg(Src0);
 
   // A span is over the clusters
   struct SearchSpan {
-    SearchSpan(SizeT Begin, SizeT Size, typename Traits::Insts::Label *Label)
+    SearchSpan(SizeT Begin, SizeT Size, InstX86Label *Label)
         : Begin(Begin), Size(Size), Label(Label) {}
 
     SizeT Begin;
     SizeT Size;
-    typename Traits::Insts::Label *Label;
+    InstX86Label *Label;
   };
   // The stack will only grow to the height of the tree so 12 should be plenty
   std::stack<SearchSpan, llvm::SmallVector<SearchSpan, 12>> SearchSpanStack;
   SearchSpanStack.emplace(0, CaseClusters.size(), nullptr);
   bool DoneCmp = false;
 
   while (!SearchSpanStack.empty()) {
     SearchSpan Span = SearchSpanStack.top();
     SearchSpanStack.pop();
 
@@ skipping 33 matching lines @@
       DoneCmp = false;
       lowerCaseCluster(*CaseB, Comparison, DoneCmp,
                        SearchSpanStack.empty() ? nullptr : DefaultTarget);
     } break;
 
     default:
       // Pick the middle item and branch b or ae
       SizeT PivotIndex = Span.Begin + (Span.Size / 2);
       const CaseCluster &Pivot = CaseClusters[PivotIndex];
       Constant *Value = Ctx->getConstantInt32(Pivot.getLow());
-      typename Traits::Insts::Label *Label =
-          Traits::Insts::Label::create(Func, this);
+      InstX86Label *Label = InstX86Label::create(Func, this);
       _cmp(Comparison, Value);
       // TODO(ascull): does it alway have to be far?
-      _br(Traits::Cond::Br_b, Label, Traits::Insts::Br::Far);
+      _br(Traits::Cond::Br_b, Label, InstX86Br::Far);
       // Lower the left and (pivot+right) sides, falling through to the right
       SearchSpanStack.emplace(Span.Begin, Span.Size / 2, Label);
       SearchSpanStack.emplace(PivotIndex, Span.Size - (Span.Size / 2), nullptr);
       DoneCmp = true;
       break;
     }
   }
 
   _br(DefaultTarget);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::scalarizeArithmetic(InstArithmetic::OpKind Kind,
-                                                 Variable *Dest, Operand *Src0,
-                                                 Operand *Src1) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::scalarizeArithmetic(InstArithmetic::OpKind Kind,
+                                                    Variable *Dest,
+                                                    Operand *Src0,
+                                                    Operand *Src1) {
   assert(isVectorType(Dest->getType()));
   Type Ty = Dest->getType();
   Type ElementTy = typeElementType(Ty);
   SizeT NumElements = typeNumElements(Ty);
 
   Operand *T = Ctx->getConstantUndef(Ty);
   for (SizeT I = 0; I < NumElements; ++I) {
     Constant *Index = Ctx->getConstantInt32(I);
 
     // Extract the next two inputs.
@@ skipping 18 matching lines @@
 }
 
 /// The following pattern occurs often in lowered C and C++ code:
 ///
 ///   %cmp     = fcmp/icmp pred <n x ty> %src0, %src1
 ///   %cmp.ext = sext <n x i1> %cmp to <n x ty>
 ///
 /// We can eliminate the sext operation by copying the result of pcmpeqd,
 /// pcmpgtd, or cmpps (which produce sign extended results) to the result of the
 /// sext operation.
-template <class Machine>
-void TargetX86Base<Machine>::eliminateNextVectorSextInstruction(
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::eliminateNextVectorSextInstruction(
     Variable *SignExtendedResult) {
   if (auto *NextCast =
           llvm::dyn_cast_or_null<InstCast>(Context.getNextInst())) {
     if (NextCast->getCastKind() == InstCast::Sext &&
         NextCast->getSrc(0) == SignExtendedResult) {
       NextCast->setDeleted();
       _movp(NextCast->getDest(), legalizeToReg(SignExtendedResult));
       // Skip over the instruction.
       Context.advanceNext();
     }
   }
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerUnreachable(
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerUnreachable(
     const InstUnreachable * /*Inst*/) {
   _ud2();
   // Add a fake use of esp to make sure esp adjustments after the unreachable
   // do not get dead-code eliminated.
   keepEspLiveAtExit();
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerRMW(
-    const typename Traits::Insts::FakeRMW *RMW) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerRMW(const InstX86FakeRMW *RMW) {
   // If the beacon variable's live range does not end in this instruction, then
   // it must end in the modified Store instruction that follows. This means
   // that the original Store instruction is still there, either because the
   // value being stored is used beyond the Store instruction, or because dead
   // code elimination did not happen. In either case, we cancel RMW lowering
   // (and the caller deletes the RMW instruction).
   if (!RMW->isLastUse(RMW->getBeacon()))
     return;
   Operand *Src = RMW->getData();
   Type Ty = Src->getType();
-  typename Traits::X86OperandMem *Addr = formMemoryOperand(RMW->getAddr(), Ty);
+  X86OperandMem *Addr = formMemoryOperand(RMW->getAddr(), Ty);
   doMockBoundsCheck(Addr);
   if (!Traits::Is64Bit && Ty == IceType_i64) {
     Src = legalizeUndef(Src);
     Operand *SrcLo = legalize(loOperand(Src), Legal_Reg | Legal_Imm);
     Operand *SrcHi = legalize(hiOperand(Src), Legal_Reg | Legal_Imm);
-    typename Traits::X86OperandMem *AddrLo =
-        llvm::cast<typename Traits::X86OperandMem>(loOperand(Addr));
-    typename Traits::X86OperandMem *AddrHi =
-        llvm::cast<typename Traits::X86OperandMem>(hiOperand(Addr));
+    X86OperandMem *AddrLo = llvm::cast<X86OperandMem>(loOperand(Addr));
+    X86OperandMem *AddrHi = llvm::cast<X86OperandMem>(hiOperand(Addr));
     switch (RMW->getOp()) {
     default:
       // TODO(stichnot): Implement other arithmetic operators.
       break;
     case InstArithmetic::Add:
       _add_rmw(AddrLo, SrcLo);
       _adc_rmw(AddrHi, SrcHi);
       return;
     case InstArithmetic::Sub:
       _sub_rmw(AddrLo, SrcLo);
@@ skipping 37 matching lines @@
       return;
     case InstArithmetic::Xor:
       Src = legalize(Src, Legal_Reg | Legal_Imm);
       _xor_rmw(Addr, Src);
       return;
     }
   }
   llvm::report_fatal_error("Couldn't lower RMW instruction");
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::lowerOther(const Inst *Instr) {
-  if (const auto *RMW =
-          llvm::dyn_cast<typename Traits::Insts::FakeRMW>(Instr)) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::lowerOther(const Inst *Instr) {
+  if (const auto *RMW = llvm::dyn_cast<InstX86FakeRMW>(Instr)) {
     lowerRMW(RMW);
   } else {
     TargetLowering::lowerOther(Instr);
   }
 }
 
 /// Turn an i64 Phi instruction into a pair of i32 Phi instructions, to preserve
 /// integrity of liveness analysis. Undef values are also turned into zeroes,
 /// since loOperand() and hiOperand() don't expect Undef input.
-template <class Machine> void TargetX86Base<Machine>::prelowerPhis() {
+template <typename TraitsType> void TargetX86Base<TraitsType>::prelowerPhis() {
   if (Traits::Is64Bit) {
     // On x86-64 we don't need to prelower phis -- the architecture can handle
     // 64-bit integer natively.
     return;
   }
 
   // Pause constant blinding or pooling, blinding or pooling will be done later
   // during phi lowering assignments
   BoolFlagSaver B(RandomizationPoolingPaused, true);
-  PhiLowering::prelowerPhis32Bit<TargetX86Base<Machine>>(
+  PhiLowering::prelowerPhis32Bit<TargetX86Base<TraitsType>>(
       this, Context.getNode(), Func);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::genTargetHelperCallFor(Inst *Instr) {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::genTargetHelperCallFor(Inst *Instr) {
   uint32_t StackArgumentsSize = 0;
   if (auto *Arith = llvm::dyn_cast<InstArithmetic>(Instr)) {
     const char *HelperName = nullptr;
     Variable *Dest = Arith->getDest();
     Type DestTy = Dest->getType();
     if (!Traits::Is64Bit && DestTy == IceType_i64) {
       switch (Arith->getOp()) {
       default:
         return;
       case InstArithmetic::Udiv:
@@ skipping 204 matching lines @@
     if (!isScalarFloatingType(ReturnType))
       return;
     StackArgumentsSize = typeWidthInBytes(ReturnType);
   } else {
     return;
   }
   StackArgumentsSize = Traits::applyStackAlignment(StackArgumentsSize);
   updateMaxOutArgsSizeBytes(StackArgumentsSize);
 }
 
-template <class Machine>
-uint32_t TargetX86Base<Machine>::getCallStackArgumentsSizeBytes(
+template <typename TraitsType>
+uint32_t TargetX86Base<TraitsType>::getCallStackArgumentsSizeBytes(
     const std::vector<Type> &ArgTypes, Type ReturnType) {
   uint32_t OutArgumentsSizeBytes = 0;
   uint32_t XmmArgCount = 0;
   uint32_t GprArgCount = 0;
   for (Type Ty : ArgTypes) {
     // The PNaCl ABI requires the width of arguments to be at least 32 bits.
     assert(typeWidthInBytes(Ty) >= 4);
     if (isVectorType(Ty) && XmmArgCount < Traits::X86_MAX_XMM_ARGS) {
       ++XmmArgCount;
     } else if (isScalarIntegerType(Ty) &&
@@ skipping 13 matching lines @@
   // The 32 bit ABI requires floating point values to be returned on the x87 FP
   // stack. Ensure there is enough space for the fstp/movs for floating returns.
   if (isScalarFloatingType(ReturnType)) {
     OutArgumentsSizeBytes =
         std::max(OutArgumentsSizeBytes,
                  static_cast<uint32_t>(typeWidthInBytesOnStack(ReturnType)));
   }
   return OutArgumentsSizeBytes;
 }
 
-template <class Machine>
-uint32_t
-TargetX86Base<Machine>::getCallStackArgumentsSizeBytes(const InstCall *Instr) {
+template <typename TraitsType>
+uint32_t TargetX86Base<TraitsType>::getCallStackArgumentsSizeBytes(
+    const InstCall *Instr) {
   // Build a vector of the arguments' types.
   std::vector<Type> ArgTypes;
   for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) {
     Operand *Arg = Instr->getArg(i);
     ArgTypes.emplace_back(Arg->getType());
   }
   // Compute the return type (if any);
   Type ReturnType = IceType_void;
   Variable *Dest = Instr->getDest();
   if (Dest != nullptr)
     ReturnType = Dest->getType();
   return getCallStackArgumentsSizeBytes(ArgTypes, ReturnType);
 }
 
-template <class Machine>
-Variable *TargetX86Base<Machine>::makeZeroedRegister(Type Ty, int32_t RegNum) {
+template <typename TraitsType>
+Variable *TargetX86Base<TraitsType>::makeZeroedRegister(Type Ty,
+                                                        int32_t RegNum) {
   Variable *Reg = makeReg(Ty, RegNum);
   switch (Ty) {
   case IceType_i1:
   case IceType_i8:
   case IceType_i16:
   case IceType_i32:
   case IceType_i64:
     // Conservatively do "mov reg, 0" to avoid modifying FLAGS.
     _mov(Reg, Ctx->getConstantZero(Ty));
     break;
@@ skipping 12 matching lines @@
   return Reg;
 }
 
 // There is no support for loading or emitting vector constants, so the vector
 // values returned from makeVectorOfZeros, makeVectorOfOnes, etc. are
 // initialized with register operations.
 //
 // TODO(wala): Add limited support for vector constants so that complex
 // initialization in registers is unnecessary.
 
-template <class Machine>
-Variable *TargetX86Base<Machine>::makeVectorOfZeros(Type Ty, int32_t RegNum) {
+template <typename TraitsType>
+Variable *TargetX86Base<TraitsType>::makeVectorOfZeros(Type Ty,
+                                                       int32_t RegNum) {
   return makeZeroedRegister(Ty, RegNum);
 }
 
-template <class Machine>
-Variable *TargetX86Base<Machine>::makeVectorOfMinusOnes(Type Ty,
-                                                        int32_t RegNum) {
+template <typename TraitsType>
+Variable *TargetX86Base<TraitsType>::makeVectorOfMinusOnes(Type Ty,
+                                                           int32_t RegNum) {
   Variable *MinusOnes = makeReg(Ty, RegNum);
   // Insert a FakeDef so the live range of MinusOnes is not overestimated.
   Context.insert<InstFakeDef>(MinusOnes);
   _pcmpeq(MinusOnes, MinusOnes);
   return MinusOnes;
 }
 
-template <class Machine>
-Variable *TargetX86Base<Machine>::makeVectorOfOnes(Type Ty, int32_t RegNum) {
+template <typename TraitsType>
+Variable *TargetX86Base<TraitsType>::makeVectorOfOnes(Type Ty, int32_t RegNum) {
   Variable *Dest = makeVectorOfZeros(Ty, RegNum);
   Variable *MinusOne = makeVectorOfMinusOnes(Ty);
   _psub(Dest, MinusOne);
   return Dest;
 }
 
-template <class Machine>
-Variable *TargetX86Base<Machine>::makeVectorOfHighOrderBits(Type Ty,
-                                                            int32_t RegNum) {
+template <typename TraitsType>
+Variable *TargetX86Base<TraitsType>::makeVectorOfHighOrderBits(Type Ty,
+                                                               int32_t RegNum) {
   assert(Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v8i16 ||
          Ty == IceType_v16i8);
   if (Ty == IceType_v4f32 || Ty == IceType_v4i32 || Ty == IceType_v8i16) {
     Variable *Reg = makeVectorOfOnes(Ty, RegNum);
     SizeT Shift =
         typeWidthInBytes(typeElementType(Ty)) * Traits::X86_CHAR_BIT - 1;
     _psll(Reg, Ctx->getConstantInt8(Shift));
     return Reg;
   } else {
     // SSE has no left shift operation for vectors of 8 bit integers.
     constexpr uint32_t HIGH_ORDER_BITS_MASK = 0x80808080;
     Constant *ConstantMask = Ctx->getConstantInt32(HIGH_ORDER_BITS_MASK);
     Variable *Reg = makeReg(Ty, RegNum);
     _movd(Reg, legalize(ConstantMask, Legal_Reg | Legal_Mem));
     _pshufd(Reg, Reg, Ctx->getConstantZero(IceType_i8));
     return Reg;
   }
 }
 
 /// Construct a mask in a register that can be and'ed with a floating-point
 /// value to mask off its sign bit. The value will be <4 x 0x7fffffff> for f32
 /// and v4f32, and <2 x 0x7fffffffffffffff> for f64. Construct it as vector of
 /// ones logically right shifted one bit.
 // TODO(stichnot): Fix the wala
 // TODO: above, to represent vector constants in memory.
-template <class Machine>
-Variable *TargetX86Base<Machine>::makeVectorOfFabsMask(Type Ty,
-                                                       int32_t RegNum) {
+template <typename TraitsType>
+Variable *TargetX86Base<TraitsType>::makeVectorOfFabsMask(Type Ty,
+                                                          int32_t RegNum) {
   Variable *Reg = makeVectorOfMinusOnes(Ty, RegNum);
   _psrl(Reg, Ctx->getConstantInt8(1));
   return Reg;
 }
 
-template <class Machine>
-typename TargetX86Base<Machine>::Traits::X86OperandMem *
-TargetX86Base<Machine>::getMemoryOperandForStackSlot(Type Ty, Variable *Slot,
-                                                     uint32_t Offset) {
+template <typename TraitsType>
+typename TargetX86Base<TraitsType>::X86OperandMem *
+TargetX86Base<TraitsType>::getMemoryOperandForStackSlot(Type Ty, Variable *Slot,
+                                                        uint32_t Offset) {
   // Ensure that Loc is a stack slot.
   assert(Slot->mustNotHaveReg());
   assert(Slot->getRegNum() == Variable::NoRegister);
   // Compute the location of Loc in memory.
   // TODO(wala,stichnot): lea should not
   // be required. The address of the stack slot is known at compile time
   // (although not until after addProlog()).
   constexpr Type PointerType = IceType_i32;
   Variable *Loc = makeReg(PointerType);
   _lea(Loc, Slot);
   Constant *ConstantOffset = Ctx->getConstantInt32(Offset);
-  return Traits::X86OperandMem::create(Func, Ty, Loc, ConstantOffset);
+  return X86OperandMem::create(Func, Ty, Loc, ConstantOffset);
 }
 
 /// Lowering helper to copy a scalar integer source operand into some 8-bit GPR.
 /// Src is assumed to already be legalized.  If the source operand is known to
 /// be a memory or immediate operand, a simple mov will suffice.  But if the
 /// source operand can be a physical register, then it must first be copied into
 /// a physical register that is truncable to 8-bit, then truncated into a
 /// physical register that can receive a truncation, and finally copied into the
 /// result 8-bit register (which in general can be any 8-bit register).  For
 /// example, moving %ebp into %ah may be accomplished as:
@@ skipping 10 matching lines @@
 /// Reg_ah.
 ///
 /// Note #2.  ConstantRelocatable operands are also put through this process
 /// (not truncated directly) because our ELF emitter does R_386_32 relocations
 /// but not R_386_8 relocations.
 ///
 /// Note #3.  If Src is a Variable, the result will be an infinite-weight i8
 /// Variable with the RCX86_IsTrunc8Rcvr register class.  As such, this helper
 /// is a convenient way to prevent ah/bh/ch/dh from being an (invalid) argument
 /// to the pinsrb instruction.
-template <class Machine>
-Variable *TargetX86Base<Machine>::copyToReg8(Operand *Src, int32_t RegNum) {
+template <typename TraitsType>
+Variable *TargetX86Base<TraitsType>::copyToReg8(Operand *Src, int32_t RegNum) {
   Type Ty = Src->getType();
   assert(isScalarIntegerType(Ty));
   assert(Ty != IceType_i1);
   Variable *Reg = makeReg(IceType_i8, RegNum);
   Reg->setRegClass(RCX86_IsTrunc8Rcvr);
   if (llvm::isa<Variable>(Src) || llvm::isa<ConstantRelocatable>(Src)) {
     Variable *SrcTruncable = makeReg(Ty);
     switch (Ty) {
     case IceType_i64:
       SrcTruncable->setRegClass(RCX86_Is64To8);
@@ skipping 13 matching lines @@
     _mov(SrcTruncable, Src);
     _mov(SrcRcvr, SrcTruncable);
     Src = SrcRcvr;
   }
   _mov(Reg, Src);
   return Reg;
 }
 
 /// Helper for legalize() to emit the right code to lower an operand to a
 /// register of the appropriate type.
-template <class Machine>
-Variable *TargetX86Base<Machine>::copyToReg(Operand *Src, int32_t RegNum) {
+template <typename TraitsType>
+Variable *TargetX86Base<TraitsType>::copyToReg(Operand *Src, int32_t RegNum) {
   Type Ty = Src->getType();
   Variable *Reg = makeReg(Ty, RegNum);
   if (isVectorType(Ty)) {
     _movp(Reg, Src);
   } else {
     _mov(Reg, Src);
   }
   return Reg;
 }
 
-template <class Machine>
-Operand *TargetX86Base<Machine>::legalize(Operand *From, LegalMask Allowed,
-                                          int32_t RegNum) {
+template <typename TraitsType>
+Operand *TargetX86Base<TraitsType>::legalize(Operand *From, LegalMask Allowed,
+                                             int32_t RegNum) {
   Type Ty = From->getType();
   // Assert that a physical register is allowed. To date, all calls to
   // legalize() allow a physical register. If a physical register needs to be
   // explicitly disallowed, then new code will need to be written to force a
   // spill.
   assert(Allowed & Legal_Reg);
   // If we're asking for a specific physical register, make sure we're not
   // allowing any other operand kinds. (This could be future work, e.g. allow
   // the shl shift amount to be either an immediate or in ecx.)
   assert(RegNum == Variable::NoRegister || Allowed == Legal_Reg);
 
   // Substitute with an available infinite-weight variable if possible.  Only do
   // this when we are not asking for a specific register, and when the
   // substitution is not locked to a specific register, and when the types
   // match, in order to capture the vast majority of opportunities and avoid
   // corner cases in the lowering.
   if (RegNum == Variable::NoRegister) {
     if (Variable *Subst = getContext().availabilityGet(From)) {
       // At this point we know there is a potential substitution available.
       if (Subst->mustHaveReg() && !Subst->hasReg()) {
         // At this point we know the substitution will have a register.
         if (From->getType() == Subst->getType()) {
           // At this point we know the substitution's register is compatible.
           return Subst;
         }
       }
     }
   }
 
-  if (auto *Mem = llvm::dyn_cast<typename Traits::X86OperandMem>(From)) {
+  if (auto *Mem = llvm::dyn_cast<X86OperandMem>(From)) {
     // Before doing anything with a Mem operand, we need to ensure that the
     // Base and Index components are in physical registers.
     Variable *Base = Mem->getBase();
     Variable *Index = Mem->getIndex();
     Variable *RegBase = nullptr;
     Variable *RegIndex = nullptr;
     if (Base) {
       RegBase = llvm::cast<Variable>(
           legalize(Base, Legal_Reg | Legal_Rematerializable));
     }
     if (Index) {
       RegIndex = llvm::cast<Variable>(
           legalize(Index, Legal_Reg | Legal_Rematerializable));
     }
     if (Base != RegBase || Index != RegIndex) {
-      Mem = Traits::X86OperandMem::create(Func, Ty, RegBase, Mem->getOffset(),
-                                          RegIndex, Mem->getShift(),
-                                          Mem->getSegmentRegister());
+      Mem = X86OperandMem::create(Func, Ty, RegBase, Mem->getOffset(), RegIndex,
+                                  Mem->getShift(), Mem->getSegmentRegister());
     }
 
     // For all Memory Operands, we do randomization/pooling here
     From = randomizeOrPoolImmediate(Mem);
 
     if (!(Allowed & Legal_Mem)) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
@@ skipping 36 matching lines @@
       } else if (auto *ConstDouble = llvm::dyn_cast<ConstantDouble>(Const)) {
         if (Utils::isPositiveZero(ConstDouble->getValue()))
           return makeZeroedRegister(Ty, RegNum);
       }
       Variable *Base = nullptr;
       std::string Buffer;
       llvm::raw_string_ostream StrBuf(Buffer);
       llvm::cast<Constant>(From)->emitPoolLabel(StrBuf, Ctx);
       llvm::cast<Constant>(From)->setShouldBePooled(true);
       Constant *Offset = Ctx->getConstantSym(0, StrBuf.str(), true);
-      From = Traits::X86OperandMem::create(Func, Ty, Base, Offset);
+      From = X86OperandMem::create(Func, Ty, Base, Offset);
     }
     bool NeedsReg = false;
     if (!(Allowed & Legal_Imm) && !isScalarFloatingType(Ty))
       // Immediate specifically not allowed
       NeedsReg = true;
     if (!(Allowed & Legal_Mem) && isScalarFloatingType(Ty))
       // On x86, FP constants are lowered to mem operands.
       NeedsReg = true;
     if (NeedsReg) {
       From = copyToReg(From, RegNum);
@@ skipping 11 matching lines @@
     // - Mem is not allowed and Var isn't guaranteed a physical register, or
     // - RegNum is required and Var->getRegNum() doesn't match, or
     // - Var is a rematerializable variable and rematerializable pass-through is
     //   not allowed (in which case we need an lea instruction).
     if (MustRematerialize) {
       assert(Ty == IceType_i32);
       Variable *NewVar = makeReg(Ty, RegNum);
       // Since Var is rematerializable, the offset will be added when the lea is
       // emitted.
       constexpr Constant *NoOffset = nullptr;
-      auto *Mem = Traits::X86OperandMem::create(Func, Ty, Var, NoOffset);
+      auto *Mem = X86OperandMem::create(Func, Ty, Var, NoOffset);
       _lea(NewVar, Mem);
       From = NewVar;
     } else if ((!(Allowed & Legal_Mem) && !MustHaveRegister) ||
                (RegNum != Variable::NoRegister && RegNum != Var->getRegNum()) ||
                MustRematerialize) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
   llvm_unreachable("Unhandled operand kind in legalize()");
   return From;
 }
 
 /// Provide a trivial wrapper to legalize() for this common usage.
-template <class Machine>
-Variable *TargetX86Base<Machine>::legalizeToReg(Operand *From, int32_t RegNum) {
+template <typename TraitsType>
+Variable *TargetX86Base<TraitsType>::legalizeToReg(Operand *From,
+                                                   int32_t RegNum) {
   return llvm::cast<Variable>(legalize(From, Legal_Reg, RegNum));
 }
 
 /// Legalize undef values to concrete values.
-template <class Machine>
-Operand *TargetX86Base<Machine>::legalizeUndef(Operand *From, int32_t RegNum) {
+template <typename TraitsType>
+Operand *TargetX86Base<TraitsType>::legalizeUndef(Operand *From,
+                                                  int32_t RegNum) {
   Type Ty = From->getType();
   if (llvm::isa<ConstantUndef>(From)) {
     // Lower undefs to zero.  Another option is to lower undefs to an
     // uninitialized register; however, using an uninitialized register results
     // in less predictable code.
     //
     // If in the future the implementation is changed to lower undef values to
     // uninitialized registers, a FakeDef will be needed:
     //     Context.insert<InstFakeDef>(Reg);
     // This is in order to ensure that the live range of Reg is not
     // overestimated.  If the constant being lowered is a 64 bit value, then
     // the result should be split and the lo and hi components will need to go
     // in uninitialized registers.
     if (isVectorType(Ty))
       return makeVectorOfZeros(Ty, RegNum);
     return Ctx->getConstantZero(Ty);
   }
   return From;
 }
 
 /// For the cmp instruction, if Src1 is an immediate, or known to be a physical
 /// register, we can allow Src0 to be a memory operand. Otherwise, Src0 must be
 /// copied into a physical register. (Actually, either Src0 or Src1 can be
 /// chosen for the physical register, but unfortunately we have to commit to one
 /// or the other before register allocation.)
-template <class Machine>
-Operand *TargetX86Base<Machine>::legalizeSrc0ForCmp(Operand *Src0,
-                                                    Operand *Src1) {
+template <typename TraitsType>
+Operand *TargetX86Base<TraitsType>::legalizeSrc0ForCmp(Operand *Src0,
+                                                       Operand *Src1) {
   bool IsSrc1ImmOrReg = false;
   if (llvm::isa<Constant>(Src1)) {
     IsSrc1ImmOrReg = true;
   } else if (auto *Var = llvm::dyn_cast<Variable>(Src1)) {
     if (Var->hasReg())
       IsSrc1ImmOrReg = true;
   }
   return legalize(Src0, IsSrc1ImmOrReg ? (Legal_Reg | Legal_Mem) : Legal_Reg);
 }
 
-template <class Machine>
-typename TargetX86Base<Machine>::Traits::X86OperandMem *
-TargetX86Base<Machine>::formMemoryOperand(Operand *Opnd, Type Ty,
-                                          bool DoLegalize) {
-  auto *Mem = llvm::dyn_cast<typename Traits::X86OperandMem>(Opnd);
+template <typename TraitsType>
+typename TargetX86Base<TraitsType>::X86OperandMem *
+TargetX86Base<TraitsType>::formMemoryOperand(Operand *Opnd, Type Ty,
+                                             bool DoLegalize) {
+  auto *Mem = llvm::dyn_cast<X86OperandMem>(Opnd);
   // It may be the case that address mode optimization already creates an
-  // Traits::X86OperandMem, so in that case it wouldn't need another level of
+  // X86OperandMem, so in that case it wouldn't need another level of
   // transformation.
   if (!Mem) {
     auto *Base = llvm::dyn_cast<Variable>(Opnd);
     auto *Offset = llvm::dyn_cast<Constant>(Opnd);
     assert(Base || Offset);
     if (Offset) {
       // During memory operand building, we do not blind or pool the constant
       // offset, we will work on the whole memory operand later as one entity
       // later, this save one instruction. By turning blinding and pooling off,
       // we guarantee legalize(Offset) will return a Constant*.
       {
         BoolFlagSaver B(RandomizationPoolingPaused, true);
 
         Offset = llvm::cast<Constant>(legalize(Offset));
       }
 
       assert(llvm::isa<ConstantInteger32>(Offset) ||
              llvm::isa<ConstantRelocatable>(Offset));
     }
-    Mem = Traits::X86OperandMem::create(Func, Ty, Base, Offset);
+    Mem = X86OperandMem::create(Func, Ty, Base, Offset);
   }
   // Do legalization, which contains randomization/pooling or do
   // randomization/pooling.
-  return llvm::cast<typename Traits::X86OperandMem>(
-      DoLegalize ? legalize(Mem) : randomizeOrPoolImmediate(Mem));
+  return llvm::cast<X86OperandMem>(DoLegalize ? legalize(Mem)
+                                              : randomizeOrPoolImmediate(Mem));
 }
 
-template <class Machine>
-Variable *TargetX86Base<Machine>::makeReg(Type Type, int32_t RegNum) {
+template <typename TraitsType>
+Variable *TargetX86Base<TraitsType>::makeReg(Type Type, int32_t RegNum) {
   // There aren't any 64-bit integer registers for x86-32.
   assert(Traits::Is64Bit || Type != IceType_i64);
   Variable *Reg = Func->makeVariable(Type);
   if (RegNum == Variable::NoRegister)
     Reg->setMustHaveReg();
   else
     Reg->setRegNum(RegNum);
   return Reg;
 }
 
-template <class Machine>
-const Type TargetX86Base<Machine>::TypeForSize[] = {
+template <typename TraitsType>
+const Type TargetX86Base<TraitsType>::TypeForSize[] = {
     IceType_i8, IceType_i16, IceType_i32, IceType_f64, IceType_v16i8};
-template <class Machine>
-Type TargetX86Base<Machine>::largestTypeInSize(uint32_t Size,
-                                               uint32_t MaxSize) {
+template <typename TraitsType>
+Type TargetX86Base<TraitsType>::largestTypeInSize(uint32_t Size,
+                                                  uint32_t MaxSize) {
   assert(Size != 0);
   uint32_t TyIndex = llvm::findLastSet(Size, llvm::ZB_Undefined);
   uint32_t MaxIndex = MaxSize == NoSizeLimit
                           ? llvm::array_lengthof(TypeForSize) - 1
                           : llvm::findLastSet(MaxSize, llvm::ZB_Undefined);
   return TypeForSize[std::min(TyIndex, MaxIndex)];
 }
 
-template <class Machine>
-Type TargetX86Base<Machine>::firstTypeThatFitsSize(uint32_t Size,
-                                                   uint32_t MaxSize) {
+template <typename TraitsType>
+Type TargetX86Base<TraitsType>::firstTypeThatFitsSize(uint32_t Size,
+                                                      uint32_t MaxSize) {
   assert(Size != 0);
   uint32_t TyIndex = llvm::findLastSet(Size, llvm::ZB_Undefined);
   if (!llvm::isPowerOf2_32(Size))
     ++TyIndex;
   uint32_t MaxIndex = MaxSize == NoSizeLimit
                           ? llvm::array_lengthof(TypeForSize) - 1
                           : llvm::findLastSet(MaxSize, llvm::ZB_Undefined);
   return TypeForSize[std::min(TyIndex, MaxIndex)];
 }
 
-template <class Machine> void TargetX86Base<Machine>::postLower() {
+template <typename TraitsType> void TargetX86Base<TraitsType>::postLower() {
   if (Ctx->getFlags().getOptLevel() == Opt_m1)
     return;
   markRedefinitions();
   Context.availabilityUpdate();
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::makeRandomRegisterPermutation(
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::makeRandomRegisterPermutation(
     llvm::SmallVectorImpl<int32_t> &Permutation,
     const llvm::SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
   Traits::makeRandomRegisterPermutation(Ctx, Func, Permutation,
                                         ExcludeRegisters, Salt);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::emit(const ConstantInteger32 *C) const {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::emit(const ConstantInteger32 *C) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   Str << getConstantPrefix() << C->getValue();
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::emit(const ConstantInteger64 *C) const {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::emit(const ConstantInteger64 *C) const {
   if (!Traits::Is64Bit) {
     llvm::report_fatal_error("Not expecting to emit 64-bit integers");
   } else {
     if (!BuildDefs::dump())
       return;
     Ostream &Str = Ctx->getStrEmit();
     Str << getConstantPrefix() << C->getValue();
   }
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::emit(const ConstantFloat *C) const {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::emit(const ConstantFloat *C) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   C->emitPoolLabel(Str, Ctx);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::emit(const ConstantDouble *C) const {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::emit(const ConstantDouble *C) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   C->emitPoolLabel(Str, Ctx);
 }
 
-template <class Machine>
-void TargetX86Base<Machine>::emit(const ConstantUndef *) const {
+template <typename TraitsType>
+void TargetX86Base<TraitsType>::emit(const ConstantUndef *) const {
   llvm::report_fatal_error("undef value encountered by emitter.");
 }
 
 /// Randomize or pool an Immediate.
-template <class Machine>
-Operand *TargetX86Base<Machine>::randomizeOrPoolImmediate(Constant *Immediate,
-                                                          int32_t RegNum) {
+template <typename TraitsType>
+Operand *
+TargetX86Base<TraitsType>::randomizeOrPoolImmediate(Constant *Immediate,
+                                                    int32_t RegNum) {
   assert(llvm::isa<ConstantInteger32>(Immediate) ||
          llvm::isa<ConstantRelocatable>(Immediate));
   if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_None ||
       RandomizationPoolingPaused == true) {
     // Immediates randomization/pooling off or paused
     return Immediate;
   }
   if (Immediate->shouldBeRandomizedOrPooled(Ctx)) {
     Ctx->statsUpdateRPImms();
     if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() ==
         RPI_Randomize) {
       // blind the constant
       // FROM:
       //  imm
       // TO:
       //  insert: mov imm+cookie, Reg
       //  insert: lea -cookie[Reg], Reg
       //  => Reg
       // If we have already assigned a phy register, we must come from
       // advancedPhiLowering()=>lowerAssign(). In this case we should reuse the
       // assigned register as this assignment is that start of its use-def
       // chain. So we add RegNum argument here. Note we use 'lea' instruction
       // instead of 'xor' to avoid affecting the flags.
       Variable *Reg = makeReg(IceType_i32, RegNum);
       auto *Integer = llvm::cast<ConstantInteger32>(Immediate);
       uint32_t Value = Integer->getValue();
       uint32_t Cookie = Func->getConstantBlindingCookie();
       _mov(Reg, Ctx->getConstantInt(IceType_i32, Cookie + Value));
       Constant *Offset = Ctx->getConstantInt(IceType_i32, 0 - Cookie);
-      _lea(Reg, Traits::X86OperandMem::create(Func, IceType_i32, Reg, Offset,
-                                              nullptr, 0));
+      _lea(Reg,
+           X86OperandMem::create(Func, IceType_i32, Reg, Offset, nullptr, 0));
       if (Immediate->getType() != IceType_i32) {
         Variable *TruncReg = makeReg(Immediate->getType(), RegNum);
         _mov(TruncReg, Reg);
         return TruncReg;
       }
       return Reg;
     }
     if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_Pool) {
       // pool the constant
       // FROM:
       //  imm
       // TO:
       //  insert: mov $label, Reg
       //  => Reg
       assert(Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_Pool);
       Immediate->setShouldBePooled(true);
       // if we have already assigned a phy register, we must come from
       // advancedPhiLowering()=>lowerAssign(). In this case we should reuse the
       // assigned register as this assignment is that start of its use-def
       // chain. So we add RegNum argument here.
       Variable *Reg = makeReg(Immediate->getType(), RegNum);
       IceString Label;
       llvm::raw_string_ostream Label_stream(Label);
       Immediate->emitPoolLabel(Label_stream, Ctx);
       constexpr RelocOffsetT Offset = 0;
       constexpr bool SuppressMangling = true;
       Constant *Symbol =
           Ctx->getConstantSym(Offset, Label_stream.str(), SuppressMangling);
-      typename Traits::X86OperandMem *MemOperand =
-          Traits::X86OperandMem::create(Func, Immediate->getType(), nullptr,
-                                        Symbol);
+      X86OperandMem *MemOperand =
+          X86OperandMem::create(Func, Immediate->getType(), nullptr, Symbol);
       _mov(Reg, MemOperand);
       return Reg;
     }
     assert("Unsupported -randomize-pool-immediates option" && false);
   }
   // the constant Immediate is not eligible for blinding/pooling
   return Immediate;
 }
 
-template <class Machine>
-typename TargetX86Base<Machine>::Traits::X86OperandMem *
-TargetX86Base<Machine>::randomizeOrPoolImmediate(
-    typename Traits::X86OperandMem *MemOperand, int32_t RegNum) {
+template <typename TraitsType>
+typename TargetX86Base<TraitsType>::X86OperandMem *
+TargetX86Base<TraitsType>::randomizeOrPoolImmediate(X86OperandMem *MemOperand,
+                                                    int32_t RegNum) {
   assert(MemOperand);
   if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_None ||
       RandomizationPoolingPaused == true) {
     // immediates randomization/pooling is turned off
     return MemOperand;
   }
 
   // If this memory operand is already a randomized one, we do not randomize it
   // again.
   if (MemOperand->getRandomized())
@@ skipping 13 matching lines @@
         //  => -cookie[RegTemp, index, shift]
         uint32_t Value =
             llvm::dyn_cast<ConstantInteger32>(MemOperand->getOffset())
                 ->getValue();
         uint32_t Cookie = Func->getConstantBlindingCookie();
         Constant *Mask1 = Ctx->getConstantInt(
             MemOperand->getOffset()->getType(), Cookie + Value);
         Constant *Mask2 =
             Ctx->getConstantInt(MemOperand->getOffset()->getType(), 0 - Cookie);
 
-        typename Traits::X86OperandMem *TempMemOperand =
-            Traits::X86OperandMem::create(Func, MemOperand->getType(),
-                                          MemOperand->getBase(), Mask1);
+        X86OperandMem *TempMemOperand = X86OperandMem::create(
+            Func, MemOperand->getType(), MemOperand->getBase(), Mask1);
         // If we have already assigned a physical register, we must come from
         // advancedPhiLowering()=>lowerAssign(). In this case we should reuse
         // the assigned register as this assignment is that start of its
         // use-def chain. So we add RegNum argument here.
         Variable *RegTemp = makeReg(MemOperand->getOffset()->getType(), RegNum);
         _lea(RegTemp, TempMemOperand);
 
-        typename Traits::X86OperandMem *NewMemOperand =
-            Traits::X86OperandMem::create(Func, MemOperand->getType(), RegTemp,
-                                          Mask2, MemOperand->getIndex(),
-                                          MemOperand->getShift(),
-                                          MemOperand->getSegmentRegister());
+        X86OperandMem *NewMemOperand = X86OperandMem::create(
+            Func, MemOperand->getType(), RegTemp, Mask2, MemOperand->getIndex(),
+            MemOperand->getShift(), MemOperand->getSegmentRegister());
 
         // Label this memory operand as randomized, so we won't randomize it
         // again in case we call legalize() multiple times on this memory
         // operand.
         NewMemOperand->setRandomized(true);
         return NewMemOperand;
       }
       if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_Pool) {
         // pool the constant offset
         // FROM:
@@ skipping 13 matching lines @@
           return MemOperand;
         Variable *RegTemp = makeReg(IceType_i32);
         IceString Label;
         llvm::raw_string_ostream Label_stream(Label);
         MemOperand->getOffset()->emitPoolLabel(Label_stream, Ctx);
         MemOperand->getOffset()->setShouldBePooled(true);
         constexpr RelocOffsetT SymOffset = 0;
         constexpr bool SuppressMangling = true;
         Constant *Symbol = Ctx->getConstantSym(SymOffset, Label_stream.str(),
                                                SuppressMangling);
-        typename Traits::X86OperandMem *SymbolOperand =
-            Traits::X86OperandMem::create(
-                Func, MemOperand->getOffset()->getType(), nullptr, Symbol);
+        X86OperandMem *SymbolOperand = X86OperandMem::create(
+            Func, MemOperand->getOffset()->getType(), nullptr, Symbol);
         _mov(RegTemp, SymbolOperand);
         // If we have a base variable here, we should add the lea instruction
         // to add the value of the base variable to RegTemp. If there is no
         // base variable, we won't need this lea instruction.
         if (MemOperand->getBase()) {
-          typename Traits::X86OperandMem *CalculateOperand =
-              Traits::X86OperandMem::create(
-                  Func, MemOperand->getType(), MemOperand->getBase(), nullptr,
-                  RegTemp, 0, MemOperand->getSegmentRegister());
+          X86OperandMem *CalculateOperand = X86OperandMem::create(
+              Func, MemOperand->getType(), MemOperand->getBase(), nullptr,
+              RegTemp, 0, MemOperand->getSegmentRegister());
           _lea(RegTemp, CalculateOperand);
         }
-        typename Traits::X86OperandMem *NewMemOperand =
-            Traits::X86OperandMem::create(Func, MemOperand->getType(), RegTemp,
-                                          nullptr, MemOperand->getIndex(),
-                                          MemOperand->getShift(),
-                                          MemOperand->getSegmentRegister());
+        X86OperandMem *NewMemOperand = X86OperandMem::create(
+            Func, MemOperand->getType(), RegTemp, nullptr,
+            MemOperand->getIndex(), MemOperand->getShift(),
+            MemOperand->getSegmentRegister());
         return NewMemOperand;
       }
       assert("Unsupported -randomize-pool-immediates option" && false);
     }
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
-} // end of namespace X86Internal
+} // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H