Subzero. Code organization.

src/IceTargetLoweringX86Base.h

 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Declares the TargetLoweringX86 template class, which implements the
 /// TargetLowering base interface for the x86 architecture.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H
 #define SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H
 
 #include "IceDefs.h"
 #include "IceInst.h"
 #include "IceSwitchLowering.h"
 #include "IceTargetLowering.h"
 #include "IceTargetLoweringX86RegClass.h"
 #include "IceUtils.h"
 
 #include <array>
 #include <type_traits>
 #include <utility>
 
+#ifndef X86NAMESPACE
+#error "You must define the X86 Target namespace."
+#endif
+
 namespace Ice {
-namespace X86Internal {
+namespace X86NAMESPACE {
 
-template <class MachineTraits> class BoolFolding;
+using namespace ::Ice::X86;
 
-template <class Machine> struct MachineTraits {};
+template <typename Traits> class BoolFolding;
 
 /// TargetX86Base is a template for all X86 Targets, and it relies on the CRT
 /// pattern for generating code, delegating to actual backends target-specific
 /// lowerings (e.g., call, ret, and intrinsics.) Backends are expected to
 /// implement the following methods (which should be accessible from
 /// TargetX86Base):
 ///
 /// Operand *createNaClReadTPSrcOperand()
 ///
 /// Note: Ideally, we should be able to
 ///
-///  static_assert(std::is_base_of<TargetX86Base<Machine>, Machine>::value);
+///  static_assert(std::is_base_of<TargetX86Base<TraitsType>,
+///  Machine>::value);
 ///
 /// but that does not work: the compiler does not know that Machine inherits
 /// from TargetX86Base at this point in translation.
-template <class Machine> class TargetX86Base : public TargetLowering {
+template <typename TraitsType> class TargetX86Base : public TargetLowering {
   TargetX86Base() = delete;
   TargetX86Base(const TargetX86Base &) = delete;
   TargetX86Base &operator=(const TargetX86Base &) = delete;
 
 public:
-  using Traits = MachineTraits<Machine>;
-  using BoolFolding = ::Ice::X86Internal::BoolFolding<Traits>;
+  using Traits = TraitsType;
+  using BoolFolding = BoolFolding<Traits>;
+  using ConcreteTarget = typename Traits::ConcreteTarget;
+  using InstructionSetEnum = typename Traits::InstructionSet;
+
+  using BrCond = typename Traits::Cond::BrCond;
+  using CmppsCond = typename Traits::Cond::CmppsCond;
+
+  using X86Address = typename Traits::Address;
+  using X86Operand = typename Traits::X86Operand;
+  using X86OperandMem = typename Traits::X86OperandMem;
+  using SegmentRegisters = typename Traits::X86OperandMem::SegmentRegisters;
+  using SpillVariable = typename Traits::SpillVariable;
+
+  using InstX86Br = typename Traits::Insts::Br;
+  using InstX86FakeRMW = typename Traits::Insts::FakeRMW;
+  using InstX86Label = typename Traits::Insts::Label;
 
   ~TargetX86Base() override = default;
 
   static void staticInit();
   static TargetX86Base *create(Cfg *Func) { return new TargetX86Base(Func); }
 
   void translateOm1() override;
   void translateO2() override;
   void doLoadOpt();
   bool doBranchOpt(Inst *I, const CfgNode *NextNode) override;
@@ skipping 80 matching lines @@
   hiOperand(Operand *Operand);
   template <typename T = Traits>
   typename std::enable_if<T::Is64Bit, Operand>::type *hiOperand(Operand *) {
     llvm::report_fatal_error(
         "Hey, yo! This is x86-64. Watcha doin'? (hiOperand)");
   }
 
   void finishArgumentLowering(Variable *Arg, Variable *FramePtr,
                               size_t BasicFrameOffset, size_t StackAdjBytes,
                               size_t &InArgsSizeBytes);
-  typename Traits::Address stackVarToAsmOperand(const Variable *Var) const;
+  X86Address stackVarToAsmOperand(const Variable *Var) const;
 
-  typename Traits::InstructionSet getInstructionSet() const {
-    return InstructionSet;
-  }
+  InstructionSetEnum getInstructionSet() const { return InstructionSet; }
   Operand *legalizeUndef(Operand *From, int32_t RegNum = Variable::NoRegister);
 
 protected:
   explicit TargetX86Base(Cfg *Func);
 
   void postLower() override;
 
   void lowerAlloca(const InstAlloca *Inst) override;
   void lowerArithmetic(const InstArithmetic *Inst) override;
   void lowerAssign(const InstAssign *Inst) override;
   void lowerBr(const InstBr *Inst) override;
   void lowerCast(const InstCast *Inst) override;
   void lowerExtractElement(const InstExtractElement *Inst) override;
   void lowerFcmp(const InstFcmp *Inst) override;
   void lowerIcmp(const InstIcmp *Inst) override;
 
   void lowerIntrinsicCall(const InstIntrinsicCall *Inst) override;
   void lowerInsertElement(const InstInsertElement *Inst) override;
   void lowerLoad(const InstLoad *Inst) override;
   void lowerPhi(const InstPhi *Inst) override;
   void lowerSelect(const InstSelect *Inst) override;
   void lowerStore(const InstStore *Inst) override;
   void lowerSwitch(const InstSwitch *Inst) override;
   void lowerUnreachable(const InstUnreachable *Inst) override;
   void lowerOther(const Inst *Instr) override;
-  void lowerRMW(const typename Traits::Insts::FakeRMW *RMW);
+  void lowerRMW(const InstX86FakeRMW *RMW);
   void prelowerPhis() override;
   uint32_t getCallStackArgumentsSizeBytes(const std::vector<Type> &ArgTypes,
                                           Type ReturnType);
   uint32_t getCallStackArgumentsSizeBytes(const InstCall *Instr) override;
   void genTargetHelperCallFor(Inst *Instr) override;
   void doAddressOptLoad() override;
   void doAddressOptStore() override;
   void doMockBoundsCheck(Operand *Opnd) override;
   void randomlyInsertNop(float Probability,
                          RandomNumberGenerator &RNG) override;
@@ skipping 70 matching lines @@
   };
   using LegalMask = uint32_t;
   Operand *legalize(Operand *From, LegalMask Allowed = Legal_All,
                     int32_t RegNum = Variable::NoRegister);
   Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister);
   /// Legalize the first source operand for use in the cmp instruction.
   Operand *legalizeSrc0ForCmp(Operand *Src0, Operand *Src1);
   /// Turn a pointer operand into a memory operand that can be used by a real
   /// load/store operation. Legalizes the operand as well. This is a nop if the
   /// operand is already a legal memory operand.
-  typename Traits::X86OperandMem *formMemoryOperand(Operand *Ptr, Type Ty,
-                                                    bool DoLegalize = true);
+  X86OperandMem *formMemoryOperand(Operand *Ptr, Type Ty,
+                                   bool DoLegalize = true);
 
   Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister);
   static Type stackSlotType();
 
   static constexpr uint32_t NoSizeLimit = 0;
   static const Type TypeForSize[];
   /// Returns the largest type which is equal to or larger than Size bytes. The
   /// type is suitable for copying memory i.e. a load and store will be a single
   /// instruction (for example x86 will get f64 not i64).
   static Type largestTypeInSize(uint32_t Size, uint32_t MaxSize = NoSizeLimit);
@@ skipping 17 matching lines @@
   Variable *makeVectorOfOnes(Type Ty, int32_t RegNum = Variable::NoRegister);
   Variable *makeVectorOfMinusOnes(Type Ty,
                                   int32_t RegNum = Variable::NoRegister);
   Variable *makeVectorOfHighOrderBits(Type Ty,
                                       int32_t RegNum = Variable::NoRegister);
   Variable *makeVectorOfFabsMask(Type Ty,
                                  int32_t RegNum = Variable::NoRegister);
   /// @}
 
   /// Return a memory operand corresponding to a stack allocated Variable.
-  typename Traits::X86OperandMem *
-  getMemoryOperandForStackSlot(Type Ty, Variable *Slot, uint32_t Offset = 0);
+  X86OperandMem *getMemoryOperandForStackSlot(Type Ty, Variable *Slot,
+                                              uint32_t Offset = 0);
 
   void
   makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation,
                                 const llvm::SmallBitVector &ExcludeRegisters,
                                 uint64_t Salt) const override;
 
   /// The following are helpers that insert lowered x86 instructions with
   /// minimal syntactic overhead, so that the lowering code can look as close to
   /// assembly as practical.
   void _adc(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Adc>(Dest, Src0);
   }
-  void _adc_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
+  void _adc_rmw(X86OperandMem *DestSrc0, Operand *Src1) {
     Context.insert<typename Traits::Insts::AdcRMW>(DestSrc0, Src1);
   }
   void _add(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Add>(Dest, Src0);
   }
-  void _add_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
+  void _add_rmw(X86OperandMem *DestSrc0, Operand *Src1) {
     Context.insert<typename Traits::Insts::AddRMW>(DestSrc0, Src1);
   }
   void _addps(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Addps>(Dest, Src0);
   }
   void _addss(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Addss>(Dest, Src0);
   }
   void _and(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::And>(Dest, Src0);
   }
   void _andnps(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Andnps>(Dest, Src0);
   }
   void _andps(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Andps>(Dest, Src0);
   }
-  void _and_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
+  void _and_rmw(X86OperandMem *DestSrc0, Operand *Src1) {
     Context.insert<typename Traits::Insts::AndRMW>(DestSrc0, Src1);
   }
   void _blendvps(Variable *Dest, Operand *Src0, Operand *Src1) {
     Context.insert<typename Traits::Insts::Blendvps>(Dest, Src0, Src1);
   }
-  void _br(typename Traits::Cond::BrCond Condition, CfgNode *TargetTrue,
-           CfgNode *TargetFalse) {
-    Context.insert<typename Traits::Insts::Br>(
-        TargetTrue, TargetFalse, Condition, Traits::Insts::Br::Far);
+  void _br(BrCond Condition, CfgNode *TargetTrue, CfgNode *TargetFalse) {
+    Context.insert<InstX86Br>(TargetTrue, TargetFalse, Condition,
+                              InstX86Br::Far);
   }
   void _br(CfgNode *Target) {
-    Context.insert<typename Traits::Insts::Br>(Target, Traits::Insts::Br::Far);
+    Context.insert<InstX86Br>(Target, InstX86Br::Far);
   }
-  void _br(typename Traits::Cond::BrCond Condition, CfgNode *Target) {
-    Context.insert<typename Traits::Insts::Br>(Target, Condition,
-                                               Traits::Insts::Br::Far);
+  void _br(BrCond Condition, CfgNode *Target) {
+    Context.insert<InstX86Br>(Target, Condition, InstX86Br::Far);
   }
-  void _br(typename Traits::Cond::BrCond Condition,
-           typename Traits::Insts::Label *Label,
-           typename Traits::Insts::Br::Mode Kind = Traits::Insts::Br::Near) {
-    Context.insert<typename Traits::Insts::Br>(Label, Condition, Kind);
+  void _br(BrCond Condition, InstX86Label *Label,
+           typename InstX86Br::Mode Kind = InstX86Br::Near) {
+    Context.insert<InstX86Br>(Label, Condition, Kind);
   }
   void _bsf(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Bsf>(Dest, Src0);
   }
   void _bsr(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Bsr>(Dest, Src0);
   }
   void _bswap(Variable *SrcDest) {
     Context.insert<typename Traits::Insts::Bswap>(SrcDest);
   }
   void _cbwdq(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Cbwdq>(Dest, Src0);
   }
-  void _cmov(Variable *Dest, Operand *Src0,
-             typename Traits::Cond::BrCond Condition) {
+  void _cmov(Variable *Dest, Operand *Src0, BrCond Condition) {
     Context.insert<typename Traits::Insts::Cmov>(Dest, Src0, Condition);
   }
   void _cmp(Operand *Src0, Operand *Src1) {
     Context.insert<typename Traits::Insts::Icmp>(Src0, Src1);
   }
-  void _cmpps(Variable *Dest, Operand *Src0,
-              typename Traits::Cond::CmppsCond Condition) {
+  void _cmpps(Variable *Dest, Operand *Src0, CmppsCond Condition) {
     Context.insert<typename Traits::Insts::Cmpps>(Dest, Src0, Condition);
   }
   void _cmpxchg(Operand *DestOrAddr, Variable *Eax, Variable *Desired,
                 bool Locked) {
     Context.insert<typename Traits::Insts::Cmpxchg>(DestOrAddr, Eax, Desired,
                                                     Locked);
     // Mark eax as possibly modified by cmpxchg.
     Context.insert<InstFakeDef>(Eax, llvm::dyn_cast<Variable>(DestOrAddr));
     _set_dest_redefined();
     Context.insert<InstFakeUse>(Eax);
   }
-  void _cmpxchg8b(typename Traits::X86OperandMem *Addr, Variable *Edx,
-                  Variable *Eax, Variable *Ecx, Variable *Ebx, bool Locked) {
+  void _cmpxchg8b(X86OperandMem *Addr, Variable *Edx, Variable *Eax,
+                  Variable *Ecx, Variable *Ebx, bool Locked) {
     Context.insert<typename Traits::Insts::Cmpxchg8b>(Addr, Edx, Eax, Ecx, Ebx,
                                                       Locked);
     // Mark edx, and eax as possibly modified by cmpxchg8b.
     Context.insert<InstFakeDef>(Edx);
     _set_dest_redefined();
     Context.insert<InstFakeUse>(Edx);
     Context.insert<InstFakeDef>(Eax);
     _set_dest_redefined();
     Context.insert<InstFakeUse>(Eax);
   }
@@ skipping 102 matching lines @@
   }
   void _nop(SizeT Variant) {
     Context.insert<typename Traits::Insts::Nop>(Variant);
   }
   void _or(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Or>(Dest, Src0);
   }
   void _orps(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Orps>(Dest, Src0);
   }
-  void _or_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
+  void _or_rmw(X86OperandMem *DestSrc0, Operand *Src1) {
     Context.insert<typename Traits::Insts::OrRMW>(DestSrc0, Src1);
   }
   void _padd(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Padd>(Dest, Src0);
   }
   void _pand(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Pand>(Dest, Src0);
   }
   void _pandn(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Pandn>(Dest, Src0);
@@ skipping 51 matching lines @@
   }
   void _rol(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Rol>(Dest, Src0);
   }
   void _sar(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Sar>(Dest, Src0);
   }
   void _sbb(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Sbb>(Dest, Src0);
   }
-  void _sbb_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
+  void _sbb_rmw(X86OperandMem *DestSrc0, Operand *Src1) {
     Context.insert<typename Traits::Insts::SbbRMW>(DestSrc0, Src1);
   }
-  void _setcc(Variable *Dest, typename Traits::Cond::BrCond Condition) {
+  void _setcc(Variable *Dest, BrCond Condition) {
     Context.insert<typename Traits::Insts::Setcc>(Dest, Condition);
   }
   void _shl(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Shl>(Dest, Src0);
   }
   void _shld(Variable *Dest, Variable *Src0, Operand *Src1) {
     Context.insert<typename Traits::Insts::Shld>(Dest, Src0, Src1);
   }
   void _shr(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Shr>(Dest, Src0);
   }
   void _shrd(Variable *Dest, Variable *Src0, Operand *Src1) {
     Context.insert<typename Traits::Insts::Shrd>(Dest, Src0, Src1);
   }
   void _shufps(Variable *Dest, Operand *Src0, Operand *Src1) {
     Context.insert<typename Traits::Insts::Shufps>(Dest, Src0, Src1);
   }
   void _sqrtss(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Sqrtss>(Dest, Src0);
   }
-  void _store(Operand *Value, typename Traits::X86Operand *Mem) {
+  void _store(Operand *Value, X86Operand *Mem) {
     Context.insert<typename Traits::Insts::Store>(Value, Mem);
   }
-  void _storep(Variable *Value, typename Traits::X86OperandMem *Mem) {
+  void _storep(Variable *Value, X86OperandMem *Mem) {
     Context.insert<typename Traits::Insts::StoreP>(Value, Mem);
   }
-  void _storeq(Variable *Value, typename Traits::X86OperandMem *Mem) {
+  void _storeq(Variable *Value, X86OperandMem *Mem) {
     Context.insert<typename Traits::Insts::StoreQ>(Value, Mem);
   }
   void _sub(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Sub>(Dest, Src0);
   }
-  void _sub_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
+  void _sub_rmw(X86OperandMem *DestSrc0, Operand *Src1) {
     Context.insert<typename Traits::Insts::SubRMW>(DestSrc0, Src1);
   }
   void _subps(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Subps>(Dest, Src0);
   }
   void _subss(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Subss>(Dest, Src0);
   }
   void _test(Operand *Src0, Operand *Src1) {
     Context.insert<typename Traits::Insts::Test>(Src0, Src1);
@@ skipping 17 matching lines @@
     Context.insert<InstFakeDef>(Src, llvm::dyn_cast<Variable>(Dest));
     _set_dest_redefined();
     Context.insert<InstFakeUse>(Src);
   }
   void _xor(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Xor>(Dest, Src0);
   }
   void _xorps(Variable *Dest, Operand *Src0) {
     Context.insert<typename Traits::Insts::Xorps>(Dest, Src0);
   }
-  void _xor_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
+  void _xor_rmw(X86OperandMem *DestSrc0, Operand *Src1) {
     Context.insert<typename Traits::Insts::XorRMW>(DestSrc0, Src1);
   }
 
   void _iaca_start() {
     if (!BuildDefs::minimal())
       Context.insert<typename Traits::Insts::IacaStart>();
   }
   void _iaca_end() {
     if (!BuildDefs::minimal())
       Context.insert<typename Traits::Insts::IacaEnd>();
@@ skipping 17 matching lines @@
       Lowering = nullptr;
     }
 
   private:
     TargetX86Base *Lowering;
   };
 
   bool optimizeScalarMul(Variable *Dest, Operand *Src0, int32_t Src1);
   void findRMW();
 
-  typename Traits::InstructionSet InstructionSet =
-      Traits::InstructionSet::Begin;
+  InstructionSetEnum InstructionSet = Traits::InstructionSet::Begin;
   bool IsEbpBasedFrame = false;
   bool NeedsStackAlignment = false;
   size_t SpillAreaSizeBytes = 0;
   size_t FixedAllocaSizeBytes = 0;
   size_t FixedAllocaAlignBytes = 0;
   bool PrologEmitsFixedAllocas = false;
   uint32_t MaxOutArgsSizeBytes = 0;
   static std::array<llvm::SmallBitVector, RCX86_NUM> TypeToRegisterSet;
   static std::array<llvm::SmallBitVector, Traits::RegisterSet::Reg_NUM>
       RegisterAliases;
   static llvm::SmallBitVector ScratchRegs;
   llvm::SmallBitVector RegsUsed;
   std::array<VarList, IceType_NUM> PhysicalRegisters;
 
   /// Randomize a given immediate operand
   Operand *randomizeOrPoolImmediate(Constant *Immediate,
                                     int32_t RegNum = Variable::NoRegister);
-  typename Traits::X86OperandMem *
-  randomizeOrPoolImmediate(typename Traits::X86OperandMem *MemOperand,
+  X86OperandMem *
+  randomizeOrPoolImmediate(X86OperandMem *MemOperand,
                            int32_t RegNum = Variable::NoRegister);
   bool RandomizationPoolingPaused = false;
 
 private:
   /// dispatchToConcrete is the template voodoo that allows TargetX86Base to
   /// invoke methods in Machine (which inherits from TargetX86Base) without
   /// having to rely on virtual method calls. There are two overloads, one for
   /// non-void types, and one for void types. We need this becase, for non-void
   /// types, we need to return the method result, where as for void, we don't.
   /// While it is true that the code compiles without the void "version", there
   /// used to be a time when compilers would reject such code.
   ///
   /// This machinery is far from perfect. Note that, in particular, the
   /// arguments provided to dispatchToConcrete() need to match the arguments for
   /// Method **exactly** (i.e., no argument promotion is performed.)
   template <typename Ret, typename... Args>
   typename std::enable_if<!std::is_void<Ret>::value, Ret>::type
-  dispatchToConcrete(Ret (Machine::*Method)(Args...), Args &&... args) {
-    return (static_cast<Machine *>(this)->*Method)(std::forward<Args>(args)...);
+  dispatchToConcrete(Ret (ConcreteTarget::*Method)(Args...), Args &&... args) {
+    return (static_cast<ConcreteTarget *>(this)->*Method)(
+        std::forward<Args>(args)...);
   }
 
   template <typename... Args>
-  void dispatchToConcrete(void (Machine::*Method)(Args...), Args &&... args) {
-    (static_cast<Machine *>(this)->*Method)(std::forward<Args>(args)...);
+  void dispatchToConcrete(void (ConcreteTarget::*Method)(Args...),
+                          Args &&... args) {
+    (static_cast<ConcreteTarget *>(this)->*Method)(std::forward<Args>(args)...);
   }
 
   void lowerShift64(InstArithmetic::OpKind Op, Operand *Src0Lo, Operand *Src0Hi,
                     Operand *Src1Lo, Variable *DestLo, Variable *DestHi);
 
   /// Emit the code for a combined operation and consumer instruction, or set
   /// the destination variable of the operation if Consumer == nullptr.
   void lowerIcmpAndConsumer(const InstIcmp *Icmp, const Inst *Consumer);
   void lowerFcmpAndConsumer(const InstFcmp *Fcmp, const Inst *Consumer);
   void lowerArithAndConsumer(const InstArithmetic *Arith, const Inst *Consumer);
 
   /// Emit a setcc instruction if Consumer == nullptr; otherwise emit a
   /// specialized version of Consumer.
-  void setccOrConsumer(typename Traits::Cond::BrCond Condition, Variable *Dest,
-                       const Inst *Consumer);
+  void setccOrConsumer(BrCond Condition, Variable *Dest, const Inst *Consumer);
 
   /// Emit a mov [1|0] instruction if Consumer == nullptr; otherwise emit a
   /// specialized version of Consumer.
   void movOrConsumer(bool IcmpResult, Variable *Dest, const Inst *Consumer);
 
   /// Emit the code for instructions with a vector type.
   void lowerIcmpVector(const InstIcmp *Icmp);
   void lowerFcmpVector(const InstFcmp *Icmp);
   void lowerSelectVector(const InstSelect *Inst);
 
   /// Helpers for select lowering.
-  void lowerSelectMove(Variable *Dest, typename Traits::Cond::BrCond Cond,
-                       Operand *SrcT, Operand *SrcF);
-  void lowerSelectIntMove(Variable *Dest, typename Traits::Cond::BrCond Cond,
-                          Operand *SrcT, Operand *SrcF);
+  void lowerSelectMove(Variable *Dest, BrCond Cond, Operand *SrcT,
+                       Operand *SrcF);
+  void lowerSelectIntMove(Variable *Dest, BrCond Cond, Operand *SrcT,
+                          Operand *SrcF);
   /// Generic helper to move an arbitrary type from Src to Dest.
   void lowerMove(Variable *Dest, Operand *Src, bool IsRedefinition);
 
   /// Optimizations for idiom recognition.
   bool lowerOptimizeFcmpSelect(const InstFcmp *Fcmp, const InstSelect *Select);
 
   /// Complains loudly if invoked because the cpu can handle 64-bit types
   /// natively.
   template <typename T = Traits>
   typename std::enable_if<T::Is64Bit, void>::type lowerIcmp64(const InstIcmp *,
                                                               const Inst *) {
     llvm::report_fatal_error(
         "Hey, yo! This is x86-64. Watcha doin'? (lowerIcmp64)");
   }
   /// x86lowerIcmp64 handles 64-bit icmp lowering.
   template <typename T = Traits>
   typename std::enable_if<!T::Is64Bit, void>::type
   lowerIcmp64(const InstIcmp *Icmp, const Inst *Consumer);
 
   BoolFolding FoldingInfo;
 };
-} // end of namespace X86Internal
+} // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #include "IceTargetLoweringX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H