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Side by Side Diff: src/IceTargetLoweringMIPS32.cpp

Issue 1548363002: Subzero. Code organization. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 11 months ago
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1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// 1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
(...skipping 14 matching lines...) Expand all
25 #include "IceLiveness.h" 25 #include "IceLiveness.h"
26 #include "IceOperand.h" 26 #include "IceOperand.h"
27 #include "IcePhiLoweringImpl.h" 27 #include "IcePhiLoweringImpl.h"
28 #include "IceRegistersMIPS32.h" 28 #include "IceRegistersMIPS32.h"
29 #include "IceTargetLoweringMIPS32.def" 29 #include "IceTargetLoweringMIPS32.def"
30 #include "IceUtils.h" 30 #include "IceUtils.h"
31 #include "llvm/Support/MathExtras.h" 31 #include "llvm/Support/MathExtras.h"
32 32
33 namespace MIPS32 { 33 namespace MIPS32 {
34 std::unique_ptr<::Ice::TargetLowering> createTargetLowering(::Ice::Cfg *Func) { 34 std::unique_ptr<::Ice::TargetLowering> createTargetLowering(::Ice::Cfg *Func) {
35 return ::Ice::TargetMIPS32::create(Func); 35 return ::Ice::MIPS32::TargetMIPS32::create(Func);
36 } 36 }
37 37
38 std::unique_ptr<::Ice::TargetDataLowering> 38 std::unique_ptr<::Ice::TargetDataLowering>
39 createTargetDataLowering(::Ice::GlobalContext *Ctx) { 39 createTargetDataLowering(::Ice::GlobalContext *Ctx) {
40 return ::Ice::TargetDataMIPS32::create(Ctx); 40 return ::Ice::MIPS32::TargetDataMIPS32::create(Ctx);
41 } 41 }
42 42
43 std::unique_ptr<::Ice::TargetHeaderLowering> 43 std::unique_ptr<::Ice::TargetHeaderLowering>
44 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) { 44 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
45 return ::Ice::TargetHeaderMIPS32::create(Ctx); 45 return ::Ice::MIPS32::TargetHeaderMIPS32::create(Ctx);
46 } 46 }
47 47
48 void staticInit() { ::Ice::TargetMIPS32::staticInit(); } 48 void staticInit() { ::Ice::MIPS32::TargetMIPS32::staticInit(); }
49 } // end of namespace MIPS32 49 } // end of namespace MIPS32
50 50
51 namespace Ice { 51 namespace Ice {
52 namespace MIPS32 {
52 53
53 using llvm::isInt; 54 using llvm::isInt;
54 55
55 namespace { 56 namespace {
56 57
57 // The maximum number of arguments to pass in GPR registers. 58 // The maximum number of arguments to pass in GPR registers.
58 constexpr uint32_t MIPS32_MAX_GPR_ARG = 4; 59 constexpr uint32_t MIPS32_MAX_GPR_ARG = 4;
59 60
60 } // end of anonymous namespace 61 } // end of anonymous namespace
61 62
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1093 Str << "\t.set\t" 1094 Str << "\t.set\t"
1094 << "nomicromips\n"; 1095 << "nomicromips\n";
1095 Str << "\t.set\t" 1096 Str << "\t.set\t"
1096 << "nomips16\n"; 1097 << "nomips16\n";
1097 } 1098 }
1098 1099
1099 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[IceType_NUM]; 1100 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[IceType_NUM];
1100 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; 1101 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
1101 llvm::SmallBitVector TargetMIPS32::ScratchRegs; 1102 llvm::SmallBitVector TargetMIPS32::ScratchRegs;
1102 1103
1104 } // end of namespace MIPS32
1103 } // end of namespace Ice 1105 } // end of namespace Ice
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