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1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
11 /// \brief Declares the TargetLoweringARM32 class, which implements the | 11 /// \brief Declares the TargetLoweringARM32 class, which implements the |
12 /// TargetLowering interface for the ARM 32-bit architecture. | 12 /// TargetLowering interface for the ARM 32-bit architecture. |
13 /// | 13 /// |
14 //===----------------------------------------------------------------------===// | 14 //===----------------------------------------------------------------------===// |
15 | 15 |
16 #ifndef SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 16 #ifndef SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
17 #define SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 17 #define SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
18 | 18 |
19 #include "IceAssemblerARM32.h" | 19 #include "IceAssemblerARM32.h" |
20 #include "IceDefs.h" | 20 #include "IceDefs.h" |
21 #include "IceInstARM32.h" | 21 #include "IceInstARM32.h" |
22 #include "IceRegistersARM32.h" | 22 #include "IceRegistersARM32.h" |
23 #include "IceTargetLowering.h" | 23 #include "IceTargetLowering.h" |
24 | 24 |
25 #include "llvm/ADT/SmallBitVector.h" | 25 #include "llvm/ADT/SmallBitVector.h" |
26 | 26 |
27 namespace Ice { | 27 namespace Ice { |
| 28 namespace ARM32 { |
28 | 29 |
29 // Class encapsulating ARM cpu features / instruction set. | 30 // Class encapsulating ARM cpu features / instruction set. |
30 class TargetARM32Features { | 31 class TargetARM32Features { |
31 TargetARM32Features() = delete; | 32 TargetARM32Features() = delete; |
32 TargetARM32Features(const TargetARM32Features &) = delete; | 33 TargetARM32Features(const TargetARM32Features &) = delete; |
33 TargetARM32Features &operator=(const TargetARM32Features &) = delete; | 34 TargetARM32Features &operator=(const TargetARM32Features &) = delete; |
34 | 35 |
35 public: | 36 public: |
36 explicit TargetARM32Features(const ClFlags &Flags); | 37 explicit TargetARM32Features(const ClFlags &Flags); |
37 | 38 |
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1199 | 1200 |
1200 protected: | 1201 protected: |
1201 explicit TargetHeaderARM32(GlobalContext *Ctx); | 1202 explicit TargetHeaderARM32(GlobalContext *Ctx); |
1202 | 1203 |
1203 private: | 1204 private: |
1204 ~TargetHeaderARM32() = default; | 1205 ~TargetHeaderARM32() = default; |
1205 | 1206 |
1206 TargetARM32Features CPUFeatures; | 1207 TargetARM32Features CPUFeatures; |
1207 }; | 1208 }; |
1208 | 1209 |
| 1210 } // end of namespace ARM32 |
1209 } // end of namespace Ice | 1211 } // end of namespace Ice |
1210 | 1212 |
1211 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 1213 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
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