Subzero. Code organization.

src/IceInstX8664.cpp

 //===- subzero/src/IceInstX8664.cpp - X86-64 instruction implementation ---===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 11 matching lines @@
 #include "IceCfg.h"
 #include "IceCfgNode.h"
 #include "IceConditionCodesX8664.h"
 #include "IceInst.h"
 #include "IceRegistersX8664.h"
 #include "IceTargetLoweringX8664.h"
 #include "IceOperand.h"
 
 namespace Ice {
 
-namespace X86Internal {
+namespace X8664 {
 
-const MachineTraits<TargetX8664>::InstBrAttributesType
-    MachineTraits<TargetX8664>::InstBrAttributes[] = {
+const TargetX8664Traits::InstBrAttributesType
+    TargetX8664Traits::InstBrAttributes[] = {
 #define X(val, encode, opp, dump, emit)                                        \
   { X8664::Traits::Cond::opp, dump, emit }                                     \
   ,
         ICEINSTX8664BR_TABLE
 #undef X
 };
 
-const MachineTraits<TargetX8664>::InstCmppsAttributesType
-    MachineTraits<TargetX8664>::InstCmppsAttributes[] = {
+const TargetX8664Traits::InstCmppsAttributesType
+    TargetX8664Traits::InstCmppsAttributes[] = {
 #define X(val, emit)                                                           \
   { emit }                                                                     \
   ,
         ICEINSTX8664CMPPS_TABLE
 #undef X
 };
 
-const MachineTraits<TargetX8664>::TypeAttributesType
-    MachineTraits<TargetX8664>::TypeAttributes[] = {
+const TargetX8664Traits::TypeAttributesType
+    TargetX8664Traits::TypeAttributes[] = {
 #define X(tag, elementty, cvt, sdss, pdps, spsd, pack, width, fld)             \
   { cvt, sdss, pdps, spsd, pack, width, fld }                                  \
   ,
         ICETYPEX8664_TABLE
 #undef X
 };
 
-void MachineTraits<TargetX8664>::X86Operand::dump(const Cfg *,
-                                                  Ostream &Str) const {
+void TargetX8664Traits::X86Operand::dump(const Cfg *, Ostream &Str) const {
   if (BuildDefs::dump())
     Str << "<OperandX8664>";
 }
 
-MachineTraits<TargetX8664>::X86OperandMem::X86OperandMem(Cfg *Func, Type Ty,
-                                                         Variable *Base,
-                                                         Constant *Offset,
-                                                         Variable *Index,
-                                                         uint16_t Shift)
+TargetX8664Traits::X86OperandMem::X86OperandMem(Cfg *Func, Type Ty,
+                                                Variable *Base,
+                                                Constant *Offset,
+                                                Variable *Index, uint16_t Shift)
     : X86Operand(kMem, Ty), Base(Base), Offset(Offset), Index(Index),
       Shift(Shift) {
   assert(Shift <= 3);
   Vars = nullptr;
   NumVars = 0;
   if (Base)
     ++NumVars;
   if (Index)
     ++NumVars;
   if (NumVars) {
     Vars = Func->allocateArrayOf<Variable *>(NumVars);
     SizeT I = 0;
     if (Base)
       Vars[I++] = Base;
     if (Index)
       Vars[I++] = Index;
     assert(I == NumVars);
   }
 }
 
 namespace {
-static int32_t getRematerializableOffset(Variable *Var,
-                                         const Ice::TargetX8664 *Target) {
+static int32_t
+getRematerializableOffset(Variable *Var,
+                          const ::Ice::X8664::TargetX8664 *Target) {
   int32_t Disp = Var->getStackOffset();
   SizeT RegNum = static_cast<SizeT>(Var->getRegNum());
   if (RegNum == Target->getFrameReg()) {
     Disp += Target->getFrameFixedAllocaOffset();
   } else if (RegNum != Target->getStackReg()) {
     llvm::report_fatal_error("Unexpected rematerializable register type");
   }
   return Disp;
 }
 } // end of anonymous namespace
 
-void MachineTraits<TargetX8664>::X86OperandMem::emit(const Cfg *Func) const {
+void TargetX8664Traits::X86OperandMem::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
-  const auto *Target = static_cast<const Ice::TargetX8664 *>(Func->getTarget());
+  const auto *Target =
+      static_cast<const ::Ice::X8664::TargetX8664 *>(Func->getTarget());
   // If the base is rematerializable, we need to replace it with the correct
   // physical register (stack or base pointer), and update the Offset.
   int32_t Disp = 0;
   if (getBase() && getBase()->isRematerializable()) {
     Disp += getRematerializableOffset(getBase(), Target);
   }
   // The index should never be rematerializable.  But if we ever allow it, then
   // we should make sure the rematerialization offset is shifted by the Shift
   // value.
   if (getIndex())
@@ skipping 37 matching lines @@
       assert(Index->getType() == IceType_i32);
       Str << ",";
       Index->emit(Func);
       if (Shift)
         Str << "," << (1u << Shift);
     }
     Str << ")";
   }
 }
 
-void MachineTraits<TargetX8664>::X86OperandMem::dump(const Cfg *Func,
-                                                     Ostream &Str) const {
+void TargetX8664Traits::X86OperandMem::dump(const Cfg *Func,
+                                            Ostream &Str) const {
   if (!BuildDefs::dump())
     return;
   bool Dumped = false;
   Str << "[";
   int32_t Disp = 0;
-  const auto *Target = static_cast<const Ice::TargetX8664 *>(Func->getTarget());
+  const auto *Target =
+      static_cast<const ::Ice::X8664::TargetX8664 *>(Func->getTarget());
   if (getBase() && getBase()->isRematerializable()) {
     Disp += getRematerializableOffset(getBase(), Target);
   }
   if (Base) {
     if (Func)
       Base->dump(Func);
     else
       Base->dump(Str);
     Dumped = true;
   }
@@ skipping 31 matching lines @@
         Str << "+";
       Offset->dump(Func, Str);
     }
   } else {
     // There is only the offset.
     Offset->dump(Func, Str);
   }
   Str << "]";
 }
 
-MachineTraits<TargetX8664>::Address
-MachineTraits<TargetX8664>::X86OperandMem::toAsmAddress(
-    MachineTraits<TargetX8664>::Assembler *Asm,
+TargetX8664Traits::Address TargetX8664Traits::X86OperandMem::toAsmAddress(
+    TargetX8664Traits::Assembler *Asm,
     const Ice::TargetLowering *TargetLowering) const {
-  const auto *Target = static_cast<const Ice::TargetX8664 *>(TargetLowering);
+  const auto *Target =
+      static_cast<const ::Ice::X8664::TargetX8664 *>(TargetLowering);
   int32_t Disp = 0;
   if (getBase() && getBase()->isRematerializable()) {
     Disp += getRematerializableOffset(getBase(), Target);
   }
   if (getIndex())
     assert(!getIndex()->isRematerializable());
   AssemblerFixup *Fixup = nullptr;
   // Determine the offset (is it relocatable?)
   if (getOffset() != nullptr) {
     if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(getOffset())) {
@@ skipping 18 matching lines @@
                                   Fixup);
   } else if (getIndex()) {
     return X8664::Traits::Address(getEncodedGPR(getIndex()->getRegNum()),
                                   X8664::Traits::ScaleFactor(getShift()), Disp,
                                   Fixup);
   } else {
     return X8664::Traits::Address(Disp, Fixup);
   }
 }
 
-MachineTraits<TargetX8664>::Address
-MachineTraits<TargetX8664>::VariableSplit::toAsmAddress(const Cfg *Func) const {
+TargetX8664Traits::Address
+TargetX8664Traits::VariableSplit::toAsmAddress(const Cfg *Func) const {
   assert(!Var->hasReg());
   const ::Ice::TargetLowering *Target = Func->getTarget();
   int32_t Offset = Var->getStackOffset() + getOffset();
   return X8664::Traits::Address(getEncodedGPR(Target->getFrameOrStackReg()),
                                 Offset, AssemblerFixup::NoFixup);
 }
 
-void MachineTraits<TargetX8664>::VariableSplit::emit(const Cfg *Func) const {
+void TargetX8664Traits::VariableSplit::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(!Var->hasReg());
   // The following is copied/adapted from TargetX8664::emitVariable().
   const ::Ice::TargetLowering *Target = Func->getTarget();
   constexpr Type Ty = IceType_i32;
   int32_t Offset = Var->getStackOffset() + getOffset();
   if (Offset)
     Str << Offset;
   Str << "(%" << Target->getRegName(Target->getFrameOrStackReg(), Ty) << ")";
 }
 
-void MachineTraits<TargetX8664>::VariableSplit::dump(const Cfg *Func,
-                                                     Ostream &Str) const {
+void TargetX8664Traits::VariableSplit::dump(const Cfg *Func,
+                                            Ostream &Str) const {
   if (!BuildDefs::dump())
     return;
   switch (Part) {
   case Low:
     Str << "low";
     break;
   case High:
     Str << "high";
     break;
   }
   Str << "(";
   if (Func)
     Var->dump(Func);
   else
     Var->dump(Str);
   Str << ")";
 }
 
-} // namespace X86Internal
+} // namespace X8664
 } // end of namespace Ice
 
-X86INSTS_DEFINE_STATIC_DATA(TargetX8664)
+X86INSTS_DEFINE_STATIC_DATA(X8664, X8664::Traits)