Subzero. Code organization.

src/IceInstX8632.cpp

 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 10 matching lines @@
 #include "IceCfg.h"
 #include "IceCfgNode.h"
 #include "IceConditionCodesX8632.h"
 #include "IceInst.h"
 #include "IceRegistersX8632.h"
 #include "IceTargetLoweringX8632.h"
 #include "IceOperand.h"
 
 namespace Ice {
 
-namespace X86Internal {
+namespace X8632 {
 
-const MachineTraits<TargetX8632>::InstBrAttributesType
-    MachineTraits<TargetX8632>::InstBrAttributes[] = {
+const TargetX8632Traits::InstBrAttributesType
+    TargetX8632Traits::InstBrAttributes[] = {
 #define X(val, encode, opp, dump, emit)                                        \
   { X8632::Traits::Cond::opp, dump, emit }                                     \
   ,
         ICEINSTX8632BR_TABLE
 #undef X
 };
 
-const MachineTraits<TargetX8632>::InstCmppsAttributesType
-    MachineTraits<TargetX8632>::InstCmppsAttributes[] = {
+const TargetX8632Traits::InstCmppsAttributesType
+    TargetX8632Traits::InstCmppsAttributes[] = {
 #define X(val, emit)                                                           \
   { emit }                                                                     \
   ,
         ICEINSTX8632CMPPS_TABLE
 #undef X
 };
 
-const MachineTraits<TargetX8632>::TypeAttributesType
-    MachineTraits<TargetX8632>::TypeAttributes[] = {
+const TargetX8632Traits::TypeAttributesType
+    TargetX8632Traits::TypeAttributes[] = {
 #define X(tag, elementty, cvt, sdss, pdps, spsd, pack, width, fld)             \
   { cvt, sdss, pdps, spsd, pack, width, fld }                                  \
   ,
         ICETYPEX8632_TABLE
 #undef X
 };
 
-const char *MachineTraits<TargetX8632>::InstSegmentRegNames[] = {
+const char *TargetX8632Traits::InstSegmentRegNames[] = {
 #define X(val, name, prefix) name,
     SEG_REGX8632_TABLE
 #undef X
 };
 
-uint8_t MachineTraits<TargetX8632>::InstSegmentPrefixes[] = {
+uint8_t TargetX8632Traits::InstSegmentPrefixes[] = {
 #define X(val, name, prefix) prefix,
     SEG_REGX8632_TABLE
 #undef X
 };
 
-void MachineTraits<TargetX8632>::X86Operand::dump(const Cfg *,
-                                                  Ostream &Str) const {
+void TargetX8632Traits::X86Operand::dump(const Cfg *, Ostream &Str) const {
   if (BuildDefs::dump())
     Str << "<OperandX8632>";
 }
 
-MachineTraits<TargetX8632>::X86OperandMem::X86OperandMem(
-    Cfg *Func, Type Ty, Variable *Base, Constant *Offset, Variable *Index,
-    uint16_t Shift, SegmentRegisters SegmentReg)
+TargetX8632Traits::X86OperandMem::X86OperandMem(Cfg *Func, Type Ty,
+                                                Variable *Base,
+                                                Constant *Offset,
+                                                Variable *Index, uint16_t Shift,
+                                                SegmentRegisters SegmentReg)
     : X86Operand(kMem, Ty), Base(Base), Offset(Offset), Index(Index),
       Shift(Shift), SegmentReg(SegmentReg), Randomized(false) {
   assert(Shift <= 3);
   Vars = nullptr;
   NumVars = 0;
   if (Base)
     ++NumVars;
   if (Index)
     ++NumVars;
   if (NumVars) {
     Vars = Func->allocateArrayOf<Variable *>(NumVars);
     SizeT I = 0;
     if (Base)
       Vars[I++] = Base;
     if (Index)
       Vars[I++] = Index;
     assert(I == NumVars);
   }
 }
 
 namespace {
-static int32_t GetRematerializableOffset(Variable *Var,
-                                         const Ice::TargetX8632 *Target) {
+static int32_t
+GetRematerializableOffset(Variable *Var,
+                          const Ice::X8632::TargetX8632 *Target) {
   int32_t Disp = Var->getStackOffset();
   SizeT RegNum = static_cast<SizeT>(Var->getRegNum());
   if (RegNum == Target->getFrameReg()) {
     Disp += Target->getFrameFixedAllocaOffset();
   } else if (RegNum != Target->getStackReg()) {
     llvm::report_fatal_error("Unexpected rematerializable register type");
   }
   return Disp;
 }
 } // end of anonymous namespace
 
-void MachineTraits<TargetX8632>::X86OperandMem::emit(const Cfg *Func) const {
+void TargetX8632Traits::X86OperandMem::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
-  const auto *Target = static_cast<const Ice::TargetX8632 *>(Func->getTarget());
+  const auto *Target =
+      static_cast<const ::Ice::X8632::TargetX8632 *>(Func->getTarget());
   // If the base is rematerializable, we need to replace it with the correct
   // physical register (esp or ebp), and update the Offset.
   int32_t Disp = 0;
   if (getBase() && getBase()->isRematerializable()) {
     Disp += GetRematerializableOffset(getBase(), Target);
   }
   // The index should never be rematerializable.  But if we ever allow it, then
   // we should make sure the rematerialization offset is shifted by the Shift
   // value.
   if (getIndex())
@@ skipping 30 matching lines @@
     if (getIndex()) {
       Str << ",";
       getIndex()->emit(Func);
       if (getShift())
         Str << "," << (1u << getShift());
     }
     Str << ")";
   }
 }
 
-void MachineTraits<TargetX8632>::X86OperandMem::dump(const Cfg *Func,
-                                                     Ostream &Str) const {
+void TargetX8632Traits::X86OperandMem::dump(const Cfg *Func,
+                                            Ostream &Str) const {
   if (!BuildDefs::dump())
     return;
   if (SegmentReg != DefaultSegment) {
     assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM);
     Str << X8632::Traits::InstSegmentRegNames[SegmentReg] << ":";
   }
   bool Dumped = false;
   Str << "[";
   int32_t Disp = 0;
-  const auto *Target = static_cast<const Ice::TargetX8632 *>(Func->getTarget());
+  const auto *Target =
+      static_cast<const ::Ice::X8632::TargetX8632 *>(Func->getTarget());
   if (getBase() && getBase()->isRematerializable()) {
     Disp += GetRematerializableOffset(getBase(), Target);
   }
   if (getBase()) {
     if (Func)
       getBase()->dump(Func);
     else
       getBase()->dump(Str);
     Dumped = true;
   }
@@ skipping 32 matching lines @@
         Str << "+";
       getOffset()->dump(Func, Str);
     }
   } else {
     // There is only the offset.
     getOffset()->dump(Func, Str);
   }
   Str << "]";
 }
 
-void MachineTraits<TargetX8632>::X86OperandMem::emitSegmentOverride(
-    MachineTraits<TargetX8632>::Assembler *Asm) const {
+void TargetX8632Traits::X86OperandMem::emitSegmentOverride(
+    TargetX8632Traits::Assembler *Asm) const {
   if (SegmentReg != DefaultSegment) {
     assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM);
     Asm->emitSegmentOverride(X8632::Traits::InstSegmentPrefixes[SegmentReg]);
   }
 }
 
-MachineTraits<TargetX8632>::Address
-MachineTraits<TargetX8632>::X86OperandMem::toAsmAddress(
-    MachineTraits<TargetX8632>::Assembler *Asm,
+TargetX8632Traits::Address TargetX8632Traits::X86OperandMem::toAsmAddress(
+    TargetX8632Traits::Assembler *Asm,
     const Ice::TargetLowering *TargetLowering) const {
   int32_t Disp = 0;
-  const auto *Target = static_cast<const Ice::TargetX8632 *>(TargetLowering);
+  const auto *Target =
+      static_cast<const ::Ice::X8632::TargetX8632 *>(TargetLowering);
   if (getBase() && getBase()->isRematerializable()) {
     Disp += GetRematerializableOffset(getBase(), Target);
   }
   // The index should never be rematerializable.  But if we ever allow it, then
   // we should make sure the rematerialization offset is shifted by the Shift
   // value.
   if (getIndex())
     assert(!getIndex()->isRematerializable());
   AssemblerFixup *Fixup = nullptr;
   // Determine the offset (is it relocatable?)
@@ skipping 20 matching lines @@
                                   Fixup);
   } else if (getIndex()) {
     return X8632::Traits::Address(getEncodedGPR(getIndex()->getRegNum()),
                                   X8632::Traits::ScaleFactor(getShift()), Disp,
                                   Fixup);
   } else {
     return X8632::Traits::Address(Disp, Fixup);
   }
 }
 
-MachineTraits<TargetX8632>::Address
-MachineTraits<TargetX8632>::VariableSplit::toAsmAddress(const Cfg *Func) const {
+TargetX8632Traits::Address
+TargetX8632Traits::VariableSplit::toAsmAddress(const Cfg *Func) const {
   assert(!Var->hasReg());
   const ::Ice::TargetLowering *Target = Func->getTarget();
   int32_t Offset = Var->getStackOffset() + getOffset();
   return X8632::Traits::Address(getEncodedGPR(Target->getFrameOrStackReg()),
                                 Offset, AssemblerFixup::NoFixup);
 }
 
-void MachineTraits<TargetX8632>::VariableSplit::emit(const Cfg *Func) const {
+void TargetX8632Traits::VariableSplit::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(!Var->hasReg());
   // The following is copied/adapted from TargetX8632::emitVariable().
   const ::Ice::TargetLowering *Target = Func->getTarget();
   constexpr Type Ty = IceType_i32;
   int32_t Offset = Var->getStackOffset() + getOffset();
   if (Offset)
     Str << Offset;
   Str << "(%" << Target->getRegName(Target->getFrameOrStackReg(), Ty) << ")";
 }
 
-void MachineTraits<TargetX8632>::VariableSplit::dump(const Cfg *Func,
-                                                     Ostream &Str) const {
+void TargetX8632Traits::VariableSplit::dump(const Cfg *Func,
+                                            Ostream &Str) const {
   if (!BuildDefs::dump())
     return;
   switch (Part) {
   case Low:
     Str << "low";
     break;
   case High:
     Str << "high";
     break;
   }
   Str << "(";
   if (Func)
     Var->dump(Func);
   else
     Var->dump(Str);
   Str << ")";
 }
 
-} // namespace X86Internal
+} // namespace X8632
 } // end of namespace Ice
 
-X86INSTS_DEFINE_STATIC_DATA(TargetX8632)
+X86INSTS_DEFINE_STATIC_DATA(X8632, X8632::Traits)