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Issue 1546373003: Subzero. X86. Refactors initRegisterSet. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fixes x86 regressions Created 4 years, 11 months ago
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1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===// 1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of lowered x86-64 instructions in the 10 // This file defines properties of lowered x86-64 instructions in the
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205 205
206 // Note: It would be more appropriate to list the xmm register aliases as 206 // Note: It would be more appropriate to list the xmm register aliases as
207 // REGLIST0(), but the corresponding empty initializer gives a syntax error, so 207 // REGLIST0(), but the corresponding empty initializer gives a syntax error, so
208 // we use REGLIST1() to redundantly assign the register itself as an alias. 208 // we use REGLIST1() to redundantly assign the register itself as an alias.
209 #define REGX8664_XMM_TABLE \ 209 #define REGX8664_XMM_TABLE \
210 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \ 210 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
211 isGPR,is64,is32,is16,is8, isXmm, \ 211 isGPR,is64,is32,is16,is8, isXmm, \
212 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \ 212 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
213 /* xmm registers */ \ 213 /* xmm registers */ \
214 X(Reg_xmm0, 0, "xmm0", Reg_xmm0, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 214 X(Reg_xmm0, 0, "xmm0", Reg_xmm0, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
215 REGLIST1(RegX8664, xmm0)) \ 215 NO_ALIASES()) \
216 X(Reg_xmm1, 1, "xmm1", Reg_xmm1, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 216 X(Reg_xmm1, 1, "xmm1", Reg_xmm1, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
217 REGLIST1(RegX8664, xmm1)) \ 217 NO_ALIASES()) \
218 X(Reg_xmm2, 2, "xmm2", Reg_xmm2, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 218 X(Reg_xmm2, 2, "xmm2", Reg_xmm2, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
219 REGLIST1(RegX8664, xmm2)) \ 219 NO_ALIASES()) \
220 X(Reg_xmm3, 3, "xmm3", Reg_xmm3, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 220 X(Reg_xmm3, 3, "xmm3", Reg_xmm3, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
221 REGLIST1(RegX8664, xmm3)) \ 221 NO_ALIASES()) \
222 X(Reg_xmm4, 4, "xmm4", Reg_xmm4, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 222 X(Reg_xmm4, 4, "xmm4", Reg_xmm4, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
223 REGLIST1(RegX8664, xmm4)) \ 223 NO_ALIASES()) \
224 X(Reg_xmm5, 5, "xmm5", Reg_xmm5, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 224 X(Reg_xmm5, 5, "xmm5", Reg_xmm5, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
225 REGLIST1(RegX8664, xmm5)) \ 225 NO_ALIASES()) \
226 X(Reg_xmm6, 6, "xmm6", Reg_xmm6, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 226 X(Reg_xmm6, 6, "xmm6", Reg_xmm6, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
227 REGLIST1(RegX8664, xmm6)) \ 227 NO_ALIASES()) \
228 X(Reg_xmm7, 7, "xmm7", Reg_xmm7, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 228 X(Reg_xmm7, 7, "xmm7", Reg_xmm7, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
229 REGLIST1(RegX8664, xmm7)) \ 229 NO_ALIASES()) \
230 X(Reg_xmm8, 8, "xmm8", Reg_xmm8, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 230 X(Reg_xmm8, 8, "xmm8", Reg_xmm8, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
231 REGLIST1(RegX8664, xmm8)) \ 231 NO_ALIASES()) \
232 X(Reg_xmm9, 9, "xmm9", Reg_xmm9, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 232 X(Reg_xmm9, 9, "xmm9", Reg_xmm9, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
233 REGLIST1(RegX8664, xmm9)) \ 233 NO_ALIASES()) \
234 X(Reg_xmm10, 10, "xmm10", Reg_xmm10, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 234 X(Reg_xmm10, 10, "xmm10", Reg_xmm10, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
235 REGLIST1(RegX8664, xmm10)) \ 235 NO_ALIASES()) \
236 X(Reg_xmm11, 11, "xmm11", Reg_xmm11, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 236 X(Reg_xmm11, 11, "xmm11", Reg_xmm11, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
237 REGLIST1(RegX8664, xmm11)) \ 237 NO_ALIASES()) \
238 X(Reg_xmm12, 12, "xmm12", Reg_xmm12, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 238 X(Reg_xmm12, 12, "xmm12", Reg_xmm12, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
239 REGLIST1(RegX8664, xmm12)) \ 239 NO_ALIASES()) \
240 X(Reg_xmm13, 13, "xmm13", Reg_xmm13, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 240 X(Reg_xmm13, 13, "xmm13", Reg_xmm13, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
241 REGLIST1(RegX8664, xmm13)) \ 241 NO_ALIASES()) \
242 X(Reg_xmm14, 14, "xmm14", Reg_xmm14, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 242 X(Reg_xmm14, 14, "xmm14", Reg_xmm14, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
243 REGLIST1(RegX8664, xmm14)) \ 243 NO_ALIASES()) \
244 X(Reg_xmm15, 15, "xmm15", Reg_xmm15, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 244 X(Reg_xmm15, 15, "xmm15", Reg_xmm15, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
245 REGLIST1(RegX8664, xmm15)) \ 245 NO_ALIASES()) \
246 /* End of xmm register set */ 246 /* End of xmm register set */
247 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, 247 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
248 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, 248 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
249 // isTrunc8Rcvr, isAhRcvr, aliases) 249 // isTrunc8Rcvr, isAhRcvr, aliases)
250 250
251 // We also provide a combined table, so that there is a namespace where 251 // We also provide a combined table, so that there is a namespace where
252 // all of the registers are considered and have distinct numberings. 252 // all of the registers are considered and have distinct numberings.
253 // This is in contrast to the above, where the "encode" is based on how 253 // This is in contrast to the above, where the "encode" is based on how
254 // the register numbers will be encoded in binaries and values can overlap. 254 // the register numbers will be encoded in binaries and values can overlap.
255 #define REGX8664_TABLE \ 255 #define REGX8664_TABLE \
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304 X(v4i1, i32, "?", "", "", "", "d", "", "") \ 304 X(v4i1, i32, "?", "", "", "", "d", "", "") \
305 X(v8i1, i16, "?", "", "", "", "w", "", "") \ 305 X(v8i1, i16, "?", "", "", "", "w", "", "") \
306 X(v16i1, i8, "?", "", "", "", "b", "", "") \ 306 X(v16i1, i8, "?", "", "", "", "b", "", "") \
307 X(v16i8, i8, "?", "", "", "", "b", "", "") \ 307 X(v16i8, i8, "?", "", "", "", "b", "", "") \
308 X(v8i16, i16, "?", "", "", "", "w", "", "") \ 308 X(v8i16, i16, "?", "", "", "", "w", "", "") \
309 X(v4i32, i32, "dq", "", "", "", "d", "", "") \ 309 X(v4i32, i32, "dq", "", "", "", "d", "", "") \
310 X(v4f32, f32, "ps", "", "ps", "ps", "d", "", "") 310 X(v4f32, f32, "ps", "", "ps", "ps", "d", "", "")
311 //#define X(tag, elementty, cvt, sdss, pdps, pack, width, fld) 311 //#define X(tag, elementty, cvt, sdss, pdps, pack, width, fld)
312 312
313 #endif // SUBZERO_SRC_ICEINSTX8664_DEF 313 #endif // SUBZERO_SRC_ICEINSTX8664_DEF
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