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Side by Side Diff: src/mips64/disasm-mips64.cc

Issue 1545013002: Add assembler test. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: rebased Created 4 years, 11 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 // A Disassembler object is used to disassemble a block of code instruction by 5 // A Disassembler object is used to disassemble a block of code instruction by
6 // instruction. The default implementation of the NameConverter object can be 6 // instruction. The default implementation of the NameConverter object can be
7 // overriden to modify register names or to do symbol lookup on addresses. 7 // overriden to modify register names or to do symbol lookup on addresses.
8 // 8 //
9 // The example below will disassemble a block of code and print it to stdout. 9 // The example below will disassemble a block of code and print it to stdout.
10 // 10 //
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68 void PrintRegister(int reg); 68 void PrintRegister(int reg);
69 void PrintFPURegister(int freg); 69 void PrintFPURegister(int freg);
70 void PrintFPUStatusRegister(int freg); 70 void PrintFPUStatusRegister(int freg);
71 void PrintRs(Instruction* instr); 71 void PrintRs(Instruction* instr);
72 void PrintRt(Instruction* instr); 72 void PrintRt(Instruction* instr);
73 void PrintRd(Instruction* instr); 73 void PrintRd(Instruction* instr);
74 void PrintFs(Instruction* instr); 74 void PrintFs(Instruction* instr);
75 void PrintFt(Instruction* instr); 75 void PrintFt(Instruction* instr);
76 void PrintFd(Instruction* instr); 76 void PrintFd(Instruction* instr);
77 void PrintSa(Instruction* instr); 77 void PrintSa(Instruction* instr);
78 void PrintLsaSa(Instruction* instr);
78 void PrintSd(Instruction* instr); 79 void PrintSd(Instruction* instr);
79 void PrintSs1(Instruction* instr); 80 void PrintSs1(Instruction* instr);
80 void PrintSs2(Instruction* instr); 81 void PrintSs2(Instruction* instr);
81 void PrintBc(Instruction* instr); 82 void PrintBc(Instruction* instr);
82 void PrintCc(Instruction* instr); 83 void PrintCc(Instruction* instr);
83 void PrintFunction(Instruction* instr); 84 void PrintFunction(Instruction* instr);
84 void PrintSecondaryField(Instruction* instr); 85 void PrintSecondaryField(Instruction* instr);
85 void PrintUImm16(Instruction* instr); 86 void PrintUImm16(Instruction* instr);
86 void PrintSImm16(Instruction* instr); 87 void PrintSImm16(Instruction* instr);
87 void PrintXImm16(Instruction* instr); 88 void PrintXImm16(Instruction* instr);
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220 } 221 }
221 222
222 223
223 // Print the integer value of the sa field. 224 // Print the integer value of the sa field.
224 void Decoder::PrintSa(Instruction* instr) { 225 void Decoder::PrintSa(Instruction* instr) {
225 int sa = instr->SaValue(); 226 int sa = instr->SaValue();
226 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa); 227 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa);
227 } 228 }
228 229
229 230
231 // Print the integer value of the sa field of a lsa instruction.
232 void Decoder::PrintLsaSa(Instruction* instr) {
233 int sa = instr->LsaSaValue() + 1;
234 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa);
235 }
236
237
230 // Print the integer value of the rd field, when it is not used as reg. 238 // Print the integer value of the rd field, when it is not used as reg.
231 void Decoder::PrintSd(Instruction* instr) { 239 void Decoder::PrintSd(Instruction* instr) {
232 int sd = instr->RdValue(); 240 int sd = instr->RdValue();
233 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sd); 241 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sd);
234 } 242 }
235 243
236 244
237 // Print the integer value of the rd field, when used as 'ext' size. 245 // Print the integer value of the rd field, when used as 'ext' size.
238 void Decoder::PrintSs1(Instruction* instr) { 246 void Decoder::PrintSs1(Instruction* instr) {
239 int ss = instr->RdValue(); 247 int ss = instr->RdValue();
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677 } 685 }
678 } 686 }
679 case 'r': { // 'r: registers. 687 case 'r': { // 'r: registers.
680 return FormatRegister(instr, format); 688 return FormatRegister(instr, format);
681 } 689 }
682 case 'f': { // 'f: FPUregisters. 690 case 'f': { // 'f: FPUregisters.
683 return FormatFPURegister(instr, format); 691 return FormatFPURegister(instr, format);
684 } 692 }
685 case 's': { // 'sa. 693 case 's': { // 'sa.
686 switch (format[1]) { 694 switch (format[1]) {
687 case 'a': { 695 case 'a':
688 DCHECK(STRING_STARTS_WITH(format, "sa")); 696 if (format[2] == '2') {
689 PrintSa(instr); 697 DCHECK(STRING_STARTS_WITH(format, "sa2")); // 'sa2
690 return 2; 698 PrintLsaSa(instr);
691 } 699 return 3;
700 } else {
701 DCHECK(STRING_STARTS_WITH(format, "sa"));
702 PrintSa(instr);
703 return 2;
704 }
705 break;
692 case 'd': { 706 case 'd': {
693 DCHECK(STRING_STARTS_WITH(format, "sd")); 707 DCHECK(STRING_STARTS_WITH(format, "sd"));
694 PrintSd(instr); 708 PrintSd(instr);
695 return 2; 709 return 2;
696 } 710 }
697 case 's': { 711 case 's': {
698 if (format[2] == '1') { 712 if (format[2] == '1') {
699 DCHECK(STRING_STARTS_WITH(format, "ss1")); /* ext size */ 713 DCHECK(STRING_STARTS_WITH(format, "ss1")); /* ext size */
700 PrintSs1(instr); 714 PrintSs1(instr);
701 return 3; 715 return 3;
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1191 Unknown(instr); 1205 Unknown(instr);
1192 } 1206 }
1193 } 1207 }
1194 break; 1208 break;
1195 case SRAV: 1209 case SRAV:
1196 Format(instr, "srav 'rd, 'rt, 'rs"); 1210 Format(instr, "srav 'rd, 'rt, 'rs");
1197 break; 1211 break;
1198 case DSRAV: 1212 case DSRAV:
1199 Format(instr, "dsrav 'rd, 'rt, 'rs"); 1213 Format(instr, "dsrav 'rd, 'rt, 'rs");
1200 break; 1214 break;
1215 case LSA:
1216 Format(instr, "lsa 'rd, 'rt, 'rs, 'sa2");
1217 break;
1218 case DLSA:
1219 Format(instr, "dlsa 'rd, 'rt, 'rs, 'sa2");
1220 break;
1201 case MFHI: 1221 case MFHI:
1202 if (instr->Bits(25, 16) == 0) { 1222 if (instr->Bits(25, 16) == 0) {
1203 Format(instr, "mfhi 'rd"); 1223 Format(instr, "mfhi 'rd");
1204 } else { 1224 } else {
1205 if ((instr->FunctionFieldRaw() == CLZ_R6) && (instr->FdValue() == 1)) { 1225 if ((instr->FunctionFieldRaw() == CLZ_R6) && (instr->FdValue() == 1)) {
1206 Format(instr, "clz 'rd, 'rs"); 1226 Format(instr, "clz 'rd, 'rs");
1207 } else if ((instr->FunctionFieldRaw() == CLO_R6) && 1227 } else if ((instr->FunctionFieldRaw() == CLO_R6) &&
1208 (instr->FdValue() == 1)) { 1228 (instr->FdValue() == 1)) {
1209 Format(instr, "clo 'rd, 'rs"); 1229 Format(instr, "clo 'rd, 'rs");
1210 } 1230 }
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1971 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); 1991 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
1972 } 1992 }
1973 } 1993 }
1974 1994
1975 1995
1976 #undef UNSUPPORTED 1996 #undef UNSUPPORTED
1977 1997
1978 } // namespace disasm 1998 } // namespace disasm
1979 1999
1980 #endif // V8_TARGET_ARCH_MIPS64 2000 #endif // V8_TARGET_ARCH_MIPS64
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