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Issue 1545013002: Add assembler test. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: rebased Created 4 years, 11 months ago
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1 1
2 // Copyright 2012 the V8 project authors. All rights reserved. 2 // Copyright 2012 the V8 project authors. All rights reserved.
3 // Use of this source code is governed by a BSD-style license that can be 3 // Use of this source code is governed by a BSD-style license that can be
4 // found in the LICENSE file. 4 // found in the LICENSE file.
5 5
6 #include <limits.h> // For LONG_MIN, LONG_MAX. 6 #include <limits.h> // For LONG_MIN, LONG_MAX.
7 7
8 #if V8_TARGET_ARCH_MIPS 8 #if V8_TARGET_ARCH_MIPS
9 9
10 #include "src/base/bits.h" 10 #include "src/base/bits.h"
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1045 1045
1046 void MacroAssembler::Pref(int32_t hint, const MemOperand& rs) { 1046 void MacroAssembler::Pref(int32_t hint, const MemOperand& rs) {
1047 if (IsMipsArchVariant(kLoongson)) { 1047 if (IsMipsArchVariant(kLoongson)) {
1048 lw(zero_reg, rs); 1048 lw(zero_reg, rs);
1049 } else { 1049 } else {
1050 pref(hint, rs); 1050 pref(hint, rs);
1051 } 1051 }
1052 } 1052 }
1053 1053
1054 1054
1055 void MacroAssembler::Lsa(Register rd, Register rt, Register rs, uint8_t sa,
1056 Register scratch) {
1057 if (IsMipsArchVariant(kMips32r6) && sa <= 4) {
1058 lsa(rd, rt, rs, sa);
1059 } else {
1060 Register tmp = rd.is(rt) ? scratch : rd;
1061 DCHECK(!tmp.is(rt));
1062 sll(tmp, rs, sa);
1063 Addu(rd, rt, tmp);
1064 }
1065 }
1066
1067
1055 // ------------Pseudo-instructions------------- 1068 // ------------Pseudo-instructions-------------
1056 1069
1057 void MacroAssembler::Ulw(Register rd, const MemOperand& rs) { 1070 void MacroAssembler::Ulw(Register rd, const MemOperand& rs) {
1058 lwr(rd, rs); 1071 lwr(rd, rs);
1059 lwl(rd, MemOperand(rs.rm(), rs.offset() + 3)); 1072 lwl(rd, MemOperand(rs.rm(), rs.offset() + 3));
1060 } 1073 }
1061 1074
1062 1075
1063 void MacroAssembler::Usw(Register rd, const MemOperand& rs) { 1076 void MacroAssembler::Usw(Register rd, const MemOperand& rs) {
1064 swr(rd, rs); 1077 swr(rd, rs);
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5753 if (mag.shift > 0) sra(result, result, mag.shift); 5766 if (mag.shift > 0) sra(result, result, mag.shift);
5754 srl(at, dividend, 31); 5767 srl(at, dividend, 31);
5755 Addu(result, result, Operand(at)); 5768 Addu(result, result, Operand(at));
5756 } 5769 }
5757 5770
5758 5771
5759 } // namespace internal 5772 } // namespace internal
5760 } // namespace v8 5773 } // namespace v8
5761 5774
5762 #endif // V8_TARGET_ARCH_MIPS 5775 #endif // V8_TARGET_ARCH_MIPS
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