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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
8 // | 8 // |
9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
10 // | 10 // |
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67 void PrintRegister(int reg); | 67 void PrintRegister(int reg); |
68 void PrintFPURegister(int freg); | 68 void PrintFPURegister(int freg); |
69 void PrintFPUStatusRegister(int freg); | 69 void PrintFPUStatusRegister(int freg); |
70 void PrintRs(Instruction* instr); | 70 void PrintRs(Instruction* instr); |
71 void PrintRt(Instruction* instr); | 71 void PrintRt(Instruction* instr); |
72 void PrintRd(Instruction* instr); | 72 void PrintRd(Instruction* instr); |
73 void PrintFs(Instruction* instr); | 73 void PrintFs(Instruction* instr); |
74 void PrintFt(Instruction* instr); | 74 void PrintFt(Instruction* instr); |
75 void PrintFd(Instruction* instr); | 75 void PrintFd(Instruction* instr); |
76 void PrintSa(Instruction* instr); | 76 void PrintSa(Instruction* instr); |
| 77 void PrintLsaSa(Instruction* instr); |
77 void PrintSd(Instruction* instr); | 78 void PrintSd(Instruction* instr); |
78 void PrintSs1(Instruction* instr); | 79 void PrintSs1(Instruction* instr); |
79 void PrintSs2(Instruction* instr); | 80 void PrintSs2(Instruction* instr); |
80 void PrintBc(Instruction* instr); | 81 void PrintBc(Instruction* instr); |
81 void PrintCc(Instruction* instr); | 82 void PrintCc(Instruction* instr); |
82 void PrintBp2(Instruction* instr); | 83 void PrintBp2(Instruction* instr); |
83 void PrintFunction(Instruction* instr); | 84 void PrintFunction(Instruction* instr); |
84 void PrintSecondaryField(Instruction* instr); | 85 void PrintSecondaryField(Instruction* instr); |
85 void PrintUImm16(Instruction* instr); | 86 void PrintUImm16(Instruction* instr); |
86 void PrintSImm16(Instruction* instr); | 87 void PrintSImm16(Instruction* instr); |
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212 } | 213 } |
213 | 214 |
214 | 215 |
215 // Print the integer value of the sa field. | 216 // Print the integer value of the sa field. |
216 void Decoder::PrintSa(Instruction* instr) { | 217 void Decoder::PrintSa(Instruction* instr) { |
217 int sa = instr->SaValue(); | 218 int sa = instr->SaValue(); |
218 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa); | 219 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa); |
219 } | 220 } |
220 | 221 |
221 | 222 |
| 223 // Print the integer value of the sa field of a lsa instruction. |
| 224 void Decoder::PrintLsaSa(Instruction* instr) { |
| 225 int sa = instr->LsaSaValue() + 1; |
| 226 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa); |
| 227 } |
| 228 |
| 229 |
222 // Print the integer value of the rd field, when it is not used as reg. | 230 // Print the integer value of the rd field, when it is not used as reg. |
223 void Decoder::PrintSd(Instruction* instr) { | 231 void Decoder::PrintSd(Instruction* instr) { |
224 int sd = instr->RdValue(); | 232 int sd = instr->RdValue(); |
225 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sd); | 233 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sd); |
226 } | 234 } |
227 | 235 |
228 | 236 |
229 // Print the integer value of the rd field, when used as 'ext' size. | 237 // Print the integer value of the rd field, when used as 'ext' size. |
230 void Decoder::PrintSs1(Instruction* instr) { | 238 void Decoder::PrintSs1(Instruction* instr) { |
231 int ss = instr->RdValue(); | 239 int ss = instr->RdValue(); |
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676 } | 684 } |
677 } | 685 } |
678 case 'r': { // 'r: registers. | 686 case 'r': { // 'r: registers. |
679 return FormatRegister(instr, format); | 687 return FormatRegister(instr, format); |
680 } | 688 } |
681 case 'f': { // 'f: FPUregisters. | 689 case 'f': { // 'f: FPUregisters. |
682 return FormatFPURegister(instr, format); | 690 return FormatFPURegister(instr, format); |
683 } | 691 } |
684 case 's': { // 'sa. | 692 case 's': { // 'sa. |
685 switch (format[1]) { | 693 switch (format[1]) { |
686 case 'a': { | 694 case 'a': |
687 DCHECK(STRING_STARTS_WITH(format, "sa")); | 695 if (format[2] == '2') { |
688 PrintSa(instr); | 696 DCHECK(STRING_STARTS_WITH(format, "sa2")); // 'sa2 |
689 return 2; | 697 PrintLsaSa(instr); |
690 } | 698 return 3; |
| 699 } else { |
| 700 DCHECK(STRING_STARTS_WITH(format, "sa")); |
| 701 PrintSa(instr); |
| 702 return 2; |
| 703 } |
| 704 break; |
691 case 'd': { | 705 case 'd': { |
692 DCHECK(STRING_STARTS_WITH(format, "sd")); | 706 DCHECK(STRING_STARTS_WITH(format, "sd")); |
693 PrintSd(instr); | 707 PrintSd(instr); |
694 return 2; | 708 return 2; |
695 } | 709 } |
696 case 's': { | 710 case 's': { |
697 if (format[2] == '1') { | 711 if (format[2] == '1') { |
698 DCHECK(STRING_STARTS_WITH(format, "ss1")); /* ext size */ | 712 DCHECK(STRING_STARTS_WITH(format, "ss1")); /* ext size */ |
699 PrintSs1(instr); | 713 PrintSs1(instr); |
700 return 3; | 714 return 3; |
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1051 if (IsMipsArchVariant(kMips32r2)) { | 1065 if (IsMipsArchVariant(kMips32r2)) { |
1052 Format(instr, "rotrv 'rd, 'rt, 'rs"); | 1066 Format(instr, "rotrv 'rd, 'rt, 'rs"); |
1053 } else { | 1067 } else { |
1054 Unknown(instr); | 1068 Unknown(instr); |
1055 } | 1069 } |
1056 } | 1070 } |
1057 break; | 1071 break; |
1058 case SRAV: | 1072 case SRAV: |
1059 Format(instr, "srav 'rd, 'rt, 'rs"); | 1073 Format(instr, "srav 'rd, 'rt, 'rs"); |
1060 break; | 1074 break; |
| 1075 case LSA: |
| 1076 Format(instr, "lsa 'rd, 'rt, 'rs, 'sa2"); |
| 1077 break; |
1061 case MFHI: | 1078 case MFHI: |
1062 if (instr->Bits(25, 16) == 0) { | 1079 if (instr->Bits(25, 16) == 0) { |
1063 Format(instr, "mfhi 'rd"); | 1080 Format(instr, "mfhi 'rd"); |
1064 } else { | 1081 } else { |
1065 if ((instr->FunctionFieldRaw() == CLZ_R6) && (instr->FdValue() == 1)) { | 1082 if ((instr->FunctionFieldRaw() == CLZ_R6) && (instr->FdValue() == 1)) { |
1066 Format(instr, "clz 'rd, 'rs"); | 1083 Format(instr, "clz 'rd, 'rs"); |
1067 } else if ((instr->FunctionFieldRaw() == CLO_R6) && | 1084 } else if ((instr->FunctionFieldRaw() == CLO_R6) && |
1068 (instr->FdValue() == 1)) { | 1085 (instr->FdValue() == 1)) { |
1069 Format(instr, "clo 'rd, 'rs"); | 1086 Format(instr, "clo 'rd, 'rs"); |
1070 } | 1087 } |
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1744 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1761 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
1745 } | 1762 } |
1746 } | 1763 } |
1747 | 1764 |
1748 | 1765 |
1749 #undef UNSUPPORTED | 1766 #undef UNSUPPORTED |
1750 | 1767 |
1751 } // namespace disasm | 1768 } // namespace disasm |
1752 | 1769 |
1753 #endif // V8_TARGET_ARCH_MIPS | 1770 #endif // V8_TARGET_ARCH_MIPS |
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