OLD | NEW |
1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include "src/ast/scopes.h" | 5 #include "src/ast/scopes.h" |
6 #include "src/compiler/code-generator.h" | 6 #include "src/compiler/code-generator.h" |
7 #include "src/compiler/code-generator-impl.h" | 7 #include "src/compiler/code-generator-impl.h" |
8 #include "src/compiler/gap-resolver.h" | 8 #include "src/compiler/gap-resolver.h" |
9 #include "src/compiler/node-matchers.h" | 9 #include "src/compiler/node-matchers.h" |
10 #include "src/compiler/osr.h" | 10 #include "src/compiler/osr.h" |
(...skipping 623 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
634 ool->entry()); | 634 ool->entry()); |
635 __ bind(ool->exit()); | 635 __ bind(ool->exit()); |
636 break; | 636 break; |
637 } | 637 } |
638 case kMips64Add: | 638 case kMips64Add: |
639 __ Addu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 639 __ Addu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); |
640 break; | 640 break; |
641 case kMips64Dadd: | 641 case kMips64Dadd: |
642 __ Daddu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 642 __ Daddu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); |
643 break; | 643 break; |
| 644 case kMips64DaddOvf: |
| 645 // Pseudo-instruction used for overflow/branch. No opcode emitted here. |
| 646 break; |
644 case kMips64Sub: | 647 case kMips64Sub: |
645 __ Subu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 648 __ Subu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); |
646 break; | 649 break; |
647 case kMips64Dsub: | 650 case kMips64Dsub: |
648 __ Dsubu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 651 __ Dsubu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); |
649 break; | 652 break; |
| 653 case kMips64DsubOvf: |
| 654 // Pseudo-instruction used for overflow/branch. No opcode emitted here. |
| 655 break; |
650 case kMips64Mul: | 656 case kMips64Mul: |
651 __ Mul(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 657 __ Mul(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); |
652 break; | 658 break; |
653 case kMips64MulHigh: | 659 case kMips64MulHigh: |
654 __ Mulh(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 660 __ Mulh(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); |
655 break; | 661 break; |
656 case kMips64MulHighU: | 662 case kMips64MulHighU: |
657 __ Mulhu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); | 663 __ Mulhu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); |
658 break; | 664 break; |
659 case kMips64DMulHigh: | 665 case kMips64DMulHigh: |
(...skipping 721 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1381 if (instr->arch_opcode() == kMips64Tst) { | 1387 if (instr->arch_opcode() == kMips64Tst) { |
1382 cc = FlagsConditionToConditionTst(branch->condition); | 1388 cc = FlagsConditionToConditionTst(branch->condition); |
1383 __ And(at, i.InputRegister(0), i.InputOperand(1)); | 1389 __ And(at, i.InputRegister(0), i.InputOperand(1)); |
1384 __ Branch(tlabel, cc, at, Operand(zero_reg)); | 1390 __ Branch(tlabel, cc, at, Operand(zero_reg)); |
1385 } else if (instr->arch_opcode() == kMips64Dadd || | 1391 } else if (instr->arch_opcode() == kMips64Dadd || |
1386 instr->arch_opcode() == kMips64Dsub) { | 1392 instr->arch_opcode() == kMips64Dsub) { |
1387 cc = FlagsConditionToConditionOvf(branch->condition); | 1393 cc = FlagsConditionToConditionOvf(branch->condition); |
1388 __ dsra32(kScratchReg, i.OutputRegister(), 0); | 1394 __ dsra32(kScratchReg, i.OutputRegister(), 0); |
1389 __ sra(at, i.OutputRegister(), 31); | 1395 __ sra(at, i.OutputRegister(), 31); |
1390 __ Branch(tlabel, cc, at, Operand(kScratchReg)); | 1396 __ Branch(tlabel, cc, at, Operand(kScratchReg)); |
| 1397 } else if (instr->arch_opcode() == kMips64DaddOvf) { |
| 1398 switch (branch->condition) { |
| 1399 case kOverflow: |
| 1400 __ DaddBranchOvf(i.OutputRegister(), i.InputRegister(0), |
| 1401 i.InputOperand(1), tlabel, flabel); |
| 1402 break; |
| 1403 case kNotOverflow: |
| 1404 __ DaddBranchOvf(i.OutputRegister(), i.InputRegister(0), |
| 1405 i.InputOperand(1), flabel, tlabel); |
| 1406 break; |
| 1407 default: |
| 1408 UNSUPPORTED_COND(kMips64DaddOvf, branch->condition); |
| 1409 break; |
| 1410 } |
| 1411 } else if (instr->arch_opcode() == kMips64DsubOvf) { |
| 1412 switch (branch->condition) { |
| 1413 case kOverflow: |
| 1414 __ DsubBranchOvf(i.OutputRegister(), i.InputRegister(0), |
| 1415 i.InputOperand(1), tlabel, flabel); |
| 1416 break; |
| 1417 case kNotOverflow: |
| 1418 __ DsubBranchOvf(i.OutputRegister(), i.InputRegister(0), |
| 1419 i.InputOperand(1), flabel, tlabel); |
| 1420 break; |
| 1421 default: |
| 1422 UNSUPPORTED_COND(kMips64DsubOvf, branch->condition); |
| 1423 break; |
| 1424 } |
1391 } else if (instr->arch_opcode() == kMips64Cmp) { | 1425 } else if (instr->arch_opcode() == kMips64Cmp) { |
1392 cc = FlagsConditionToConditionCmp(branch->condition); | 1426 cc = FlagsConditionToConditionCmp(branch->condition); |
1393 __ Branch(tlabel, cc, i.InputRegister(0), i.InputOperand(1)); | 1427 __ Branch(tlabel, cc, i.InputRegister(0), i.InputOperand(1)); |
1394 } else if (instr->arch_opcode() == kMips64CmpS) { | 1428 } else if (instr->arch_opcode() == kMips64CmpS) { |
1395 if (!convertCondition(branch->condition, cc)) { | 1429 if (!convertCondition(branch->condition, cc)) { |
1396 UNSUPPORTED_COND(kMips64CmpS, branch->condition); | 1430 UNSUPPORTED_COND(kMips64CmpS, branch->condition); |
1397 } | 1431 } |
1398 FPURegister left = i.InputOrZeroSingleRegister(0); | 1432 FPURegister left = i.InputOrZeroSingleRegister(0); |
1399 FPURegister right = i.InputOrZeroSingleRegister(1); | 1433 FPURegister right = i.InputOrZeroSingleRegister(1); |
1400 if ((left.is(kDoubleRegZero) || right.is(kDoubleRegZero)) && | 1434 if ((left.is(kDoubleRegZero) || right.is(kDoubleRegZero)) && |
(...skipping 54 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1455 } else if (instr->arch_opcode() == kMips64Dadd || | 1489 } else if (instr->arch_opcode() == kMips64Dadd || |
1456 instr->arch_opcode() == kMips64Dsub) { | 1490 instr->arch_opcode() == kMips64Dsub) { |
1457 cc = FlagsConditionToConditionOvf(condition); | 1491 cc = FlagsConditionToConditionOvf(condition); |
1458 // Check for overflow creates 1 or 0 for result. | 1492 // Check for overflow creates 1 or 0 for result. |
1459 __ dsrl32(kScratchReg, i.OutputRegister(), 31); | 1493 __ dsrl32(kScratchReg, i.OutputRegister(), 31); |
1460 __ srl(at, i.OutputRegister(), 31); | 1494 __ srl(at, i.OutputRegister(), 31); |
1461 __ xor_(result, kScratchReg, at); | 1495 __ xor_(result, kScratchReg, at); |
1462 if (cc == eq) // Toggle result for not overflow. | 1496 if (cc == eq) // Toggle result for not overflow. |
1463 __ xori(result, result, 1); | 1497 __ xori(result, result, 1); |
1464 return; | 1498 return; |
| 1499 } else if (instr->arch_opcode() == kMips64DaddOvf || |
| 1500 instr->arch_opcode() == kMips64DsubOvf) { |
| 1501 Label flabel, tlabel; |
| 1502 switch (instr->arch_opcode()) { |
| 1503 case kMips64DaddOvf: |
| 1504 __ DaddBranchNoOvf(i.OutputRegister(), i.InputRegister(0), |
| 1505 i.InputOperand(1), &flabel); |
| 1506 |
| 1507 break; |
| 1508 case kMips64DsubOvf: |
| 1509 __ DsubBranchNoOvf(i.OutputRegister(), i.InputRegister(0), |
| 1510 i.InputOperand(1), &flabel); |
| 1511 break; |
| 1512 default: |
| 1513 UNREACHABLE(); |
| 1514 break; |
| 1515 } |
| 1516 __ li(result, 1); |
| 1517 __ Branch(&tlabel); |
| 1518 __ bind(&flabel); |
| 1519 __ li(result, 0); |
| 1520 __ bind(&tlabel); |
1465 } else if (instr->arch_opcode() == kMips64Cmp) { | 1521 } else if (instr->arch_opcode() == kMips64Cmp) { |
1466 cc = FlagsConditionToConditionCmp(condition); | 1522 cc = FlagsConditionToConditionCmp(condition); |
1467 switch (cc) { | 1523 switch (cc) { |
1468 case eq: | 1524 case eq: |
1469 case ne: { | 1525 case ne: { |
1470 Register left = i.InputRegister(0); | 1526 Register left = i.InputRegister(0); |
1471 Operand right = i.InputOperand(1); | 1527 Operand right = i.InputOperand(1); |
1472 Register select; | 1528 Register select; |
1473 if (instr->InputAt(1)->IsImmediate() && right.immediate() == 0) { | 1529 if (instr->InputAt(1)->IsImmediate() && right.immediate() == 0) { |
1474 // Pass left operand if right is zero. | 1530 // Pass left operand if right is zero. |
(...skipping 441 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1916 padding_size -= v8::internal::Assembler::kInstrSize; | 1972 padding_size -= v8::internal::Assembler::kInstrSize; |
1917 } | 1973 } |
1918 } | 1974 } |
1919 } | 1975 } |
1920 | 1976 |
1921 #undef __ | 1977 #undef __ |
1922 | 1978 |
1923 } // namespace compiler | 1979 } // namespace compiler |
1924 } // namespace internal | 1980 } // namespace internal |
1925 } // namespace v8 | 1981 } // namespace v8 |
OLD | NEW |