Index: src/IceInstX8664.cpp |
diff --git a/src/IceInstX8664.cpp b/src/IceInstX8664.cpp |
index 6c8d9823ee6cd0fec55b32bbf0a6981c006c0126..c682d9e26508f87b72e3147929952466665d09a9 100644 |
--- a/src/IceInstX8664.cpp |
+++ b/src/IceInstX8664.cpp |
@@ -140,9 +140,21 @@ void MachineTraits<TargetX8664>::X86OperandMem::emit(const Cfg *Func) const { |
if (Base || Index) { |
Str << "("; |
- if (Base) |
- Base->emit(Func); |
+ if (Base) { |
+ const Variable *Base32 = Base; |
+ if (Base->getType() != IceType_i32) { |
+ // X86-64 is ILP32, but %rsp and %rbp are accessed as 64-bit registers. |
+ // For filetype=asm, they need to be emitted as their 32-bit sibilings. |
+ assert(Base->getType() == IceType_i64); |
+ assert(Base->getRegNum() == RegX8664::Encoded_Reg_rsp || |
+ Base->getRegNum() == RegX8664::Encoded_Reg_rbp); |
+ Base32 = Base->asType(IceType_i32, X8664::Traits::getGprForType( |
+ IceType_i32, Base->getRegNum())); |
+ } |
+ Base32->emit(Func); |
+ } |
if (Index) { |
+ assert(Index->getType() == IceType_i32); |
Str << ","; |
Index->emit(Func); |
if (Shift) |