Subzero. X8664. Fixes filetype=asm.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 764 matching lines @@
     Reg = Func->makeVariable(Ty);
     Reg->setRegNum(RegNum);
     PhysicalRegisters[Ty][RegNum] = Reg;
     // Specially mark a named physical register as an "argument" so that it is
     // considered live upon function entry.  Otherwise it's possible to get
     // liveness validation errors for saving callee-save registers.
     Func->addImplicitArg(Reg);
     // Don't bother tracking the live range of a named physical register.
     Reg->setIgnoreLiveness();
   }
+  assert(Traits::getGprForType(Ty, RegNum) == static_cast<int32_t>(RegNum));
   return Reg;
 }
 
 template <class Machine>
-IceString TargetX86Base<Machine>::getRegName(SizeT RegNum, Type) const {
-  return Traits::getRegName(RegNum);
+IceString TargetX86Base<Machine>::getRegName(SizeT RegNum, Type Ty) const {
+  return Traits::getRegName(Traits::getGprForType(Ty, RegNum));
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::emitVariable(const Variable *Var) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   if (Var->hasReg()) {
     Str << "%" << getRegName(Var->getRegNum(), Var->getType());
     return;
@@ skipping 186 matching lines @@
       std::max(AlignmentParam, Traits::X86_STACK_ALIGNMENT_BYTES);
   const bool OverAligned = Alignment > Traits::X86_STACK_ALIGNMENT_BYTES;
   const bool OptM1 = Ctx->getFlags().getOptLevel() == Opt_m1;
   const bool AllocaWithKnownOffset = Inst->getKnownFrameOffset();
   const bool UseFramePointer =
       hasFramePointer() || OverAligned || !AllocaWithKnownOffset || OptM1;
 
   if (UseFramePointer)
     setHasFramePointer();
 
-  Variable *esp = getPhysicalRegister(getStackReg());
+  Variable *esp = getPhysicalRegister(getStackReg(), Traits::WordType);
   if (OverAligned) {
     _and(esp, Ctx->getConstantInt32(-Alignment));
   }
 
   Variable *Dest = Inst->getDest();
   Operand *TotalSize = legalize(Inst->getSizeInBytes());
 
   if (const auto *ConstantTotalSize =
           llvm::dyn_cast<ConstantInteger32>(TotalSize)) {
     const uint32_t Value =
         Utils::applyAlignment(ConstantTotalSize->getValue(), Alignment);
     if (!UseFramePointer) {
       // If we don't need a Frame Pointer, this alloca has a known offset to the
       // stack pointer. We don't need adjust the stack pointer, nor assign any
       // value to Dest, as Dest is rematerializable.
       assert(Dest->isRematerializable());
       FixedAllocaSizeBytes += Value;
       Context.insert<InstFakeDef>(Dest);
     } else {
       _sub(esp, Ctx->getConstantInt32(Value));
     }
   } else {
     // Non-constant sizes need to be adjusted to the next highest multiple of
     // the required alignment at runtime.
-    Variable *T = makeReg(IceType_i32);
-    _mov(T, TotalSize);
+    Variable *T = makeReg(Traits::WordType);
+    if (Traits::Is64Bit && TotalSize->getType() != IceType_i64) {
+      _movzx(T, TotalSize);
+    } else {
+      _mov(T, TotalSize);
+    }
     _add(T, Ctx->getConstantInt32(Alignment - 1));
     _and(T, Ctx->getConstantInt32(-Alignment));
     _sub(esp, T);
   }
   // Add enough to the returned address to account for the out args area.
   uint32_t OutArgsSize = maxOutArgsSizeBytes();
   if (OutArgsSize > 0) {
     Variable *T = makeReg(IceType_i32);
     typename Traits::X86OperandMem *CalculateOperand =
         Traits::X86OperandMem::create(
@@ skipping 676 matching lines @@
     // immediates as the operand.
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
     uint32_t Eax;
     uint32_t Edx;
     switch (Ty) {
     default:
       llvm::report_fatal_error("Bad type for udiv");
     case IceType_i64:
       Eax = Traits::getRaxOrDie();
       Edx = Traits::getRdxOrDie();
+      break;
     case IceType_i32:
       Eax = Traits::RegisterSet::Reg_eax;
       Edx = Traits::RegisterSet::Reg_edx;
       break;
     case IceType_i16:
       Eax = Traits::RegisterSet::Reg_ax;
       Edx = Traits::RegisterSet::Reg_dx;
       break;
     case IceType_i8:
       Eax = Traits::RegisterSet::Reg_al;
       Edx = Traits::RegisterSet::Reg_ah;
       break;
     }
+    T_edx = makeReg(Ty, Edx);
     _mov(T, Src0, Eax);
-    _mov(T_edx, Ctx->getConstantZero(Ty), Edx);
+    _mov(T_edx, Ctx->getConstantZero(Ty));
     _div(T, Src1, T_edx);
     _mov(Dest, T);
   } break;
   case InstArithmetic::Sdiv:
     // TODO(stichnot): Enable this after doing better performance and cross
     // testing.
     if (false && Ctx->getFlags().getOptLevel() >= Opt_1) {
       // Optimize division by constant power of 2, but not for Om1 or O0, just
       // to keep things simple there.
       if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
@@ skipping 557 matching lines @@
       SpillVar->setLinkedTo(Dest);
       Variable *Spill = SpillVar;
       Spill->setMustNotHaveReg();
       _mov(T, Src0RM);
       _mov(Spill, T);
       _mov(Dest, Spill);
     } break;
     case IceType_i64: {
       assert(Src0->getType() == IceType_f64);
       if (Traits::Is64Bit) {
-        // Movd requires its fp argument (in this case, the bitcast source) to
-        // be an xmm register.
         Variable *Src0R = legalizeToReg(Src0);
         Variable *T = makeReg(IceType_i64);
         _movd(T, Src0R);
         _mov(Dest, T);
       } else {
         Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
         // a.i64 = bitcast b.f64 ==>
         //   s.f64 = spill b.f64
         //   t_lo.i32 = lo(s.f64)
         //   a_lo.i32 = t_lo.i32
@@ skipping 25 matching lines @@
         _mov(DestLo, T_Lo);
         _mov(T_Hi, SpillHi);
         _mov(DestHi, T_Hi);
       }
     } break;
     case IceType_f64: {
       assert(Src0->getType() == IceType_i64);
       if (Traits::Is64Bit) {
         Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
         Variable *T = makeReg(IceType_f64);
-        // Movd requires its fp argument (in this case, the bitcast
-        // destination) to be an xmm register.
         _movd(T, Src0RM);
         _mov(Dest, T);
       } else {
         Src0 = legalize(Src0);
         if (llvm::isa<typename Traits::X86OperandMem>(Src0)) {
           Variable *T = Func->makeVariable(DestTy);
           _movq(T, Src0);
           _movq(Dest, T);
           break;
         }
@@ skipping 1173 matching lines @@
   }
   case Intrinsics::Sqrt: {
     Operand *Src = legalize(Instr->getArg(0));
     Variable *Dest = Instr->getDest();
     Variable *T = makeReg(Dest->getType());
     _sqrtss(T, Src);
     _mov(Dest, T);
     return;
   }
   case Intrinsics::Stacksave: {
-    Variable *esp = Func->getTarget()->getPhysicalRegister(getStackReg());
+    Variable *esp =
+        Func->getTarget()->getPhysicalRegister(getStackReg(), Traits::WordType);
     Variable *Dest = Instr->getDest();
     _mov(Dest, esp);
     return;
   }
   case Intrinsics::Stackrestore: {
-    Variable *esp = Func->getTarget()->getPhysicalRegister(getStackReg());
-    _redefined(_mov(esp, Instr->getArg(0)));
+    Operand *Src = Instr->getArg(0);
+    const Type SrcTy = Src->getType();
+    Variable *esp = Func->getTarget()->getPhysicalRegister(
+        Traits::getGprForType(SrcTy, getStackReg()), SrcTy);
+    _redefined(_mov(esp, Src));
     return;
   }
   case Intrinsics::Trap:
     _ud2();
     return;
   case Intrinsics::UnknownIntrinsic:
     Func->setError("Should not be lowering UnknownIntrinsic");
     return;
   }
   return;
@@ skipping 682 matching lines @@
     ValExt = ValExtVar;
   }
   InstCall *Call = makeHelperCall(H_call_memset, nullptr, 3);
   Call->addArg(Dest);
   Call->addArg(ValExt);
   Call->addArg(Count);
   lowerCall(Call);
 }
 
 template <class Machine>
-void TargetX86Base<Machine>::lowerIndirectJump(Variable *Target) {
+void TargetX86Base<Machine>::lowerIndirectJump(Variable *JumpTarget) {
   const bool NeedSandboxing = Ctx->getFlags().getUseSandboxing();
+  if (Traits::Is64Bit) {
+    Variable *T = makeReg(IceType_i64);
+    _movzx(T, JumpTarget);
+    JumpTarget = T;
+  }
   if (NeedSandboxing) {
     _bundle_lock();
     const SizeT BundleSize =
         1 << Func->getAssembler<>()->getBundleAlignLog2Bytes();
-    _and(Target, Ctx->getConstantInt32(~(BundleSize - 1)));
+    _and(JumpTarget, Ctx->getConstantInt32(~(BundleSize - 1)));
   }
-  _jmp(Target);
+  _jmp(JumpTarget);
   if (NeedSandboxing)
     _bundle_unlock();
 }
 
 inline bool isAdd(const Inst *Inst) {
   if (auto *Arith = llvm::dyn_cast_or_null<const InstArithmetic>(Inst)) {
     return (Arith->getOp() == InstArithmetic::Add);
   }
   return false;
 }
@@ skipping 381 matching lines @@
     Opnd = Mem->getBase();
   }
   // At this point Opnd could be nullptr, or Variable, or Constant, or perhaps
   // something else.  We only care if it is Variable.
   auto *Var = llvm::dyn_cast_or_null<Variable>(Opnd);
   if (Var == nullptr)
     return;
   // We use lowerStore() to copy out-args onto the stack.  This creates a memory
   // operand with the stack pointer as the base register.  Don't do bounds
   // checks on that.
-  if (Var->getRegNum() == Traits::RegisterSet::Reg_esp)
+  if (Var->getRegNum() == static_cast<int32_t>(getStackReg()))
     return;
 
   auto *Label = Traits::Insts::Label::create(Func, this);
   _cmp(Opnd, Ctx->getConstantZero(IceType_i32));
   _br(Traits::Cond::Br_e, Label);
   _cmp(Opnd, Ctx->getConstantInt32(1));
   _br(Traits::Cond::Br_e, Label);
   Context.insert(Label);
 }
 
@@ skipping 1289 matching lines @@
         return From;
       Const = llvm::cast<Constant>(From);
     }
     // There should be no constants of vector type (other than undef).
     assert(!isVectorType(Ty));
 
     // If the operand is a 64 bit constant integer we need to legalize it to a
     // register in x86-64.
     if (Traits::Is64Bit) {
       if (llvm::isa<ConstantInteger64>(Const)) {
-        Variable *V = copyToReg(Const, RegNum);
-        return V;
+        if (RegNum != Variable::NoRegister) {
+          assert(Traits::getGprForType(IceType_i64, RegNum) == RegNum);
+        }
+        return copyToReg(Const, RegNum);
       }
     }
 
     // If the operand is an 32 bit constant integer, we should check whether we
     // need to randomize it or pool it.
     if (auto *C = llvm::dyn_cast<ConstantInteger32>(Const)) {
       Operand *NewConst = randomizeOrPoolImmediate(C, RegNum);
       if (NewConst != Const) {
         return NewConst;
       }
@@ skipping 423 matching lines @@
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H