Subzero. X8664. Fixes filetype=asm.

src/IceInstX86BaseImpl.h

 //===- subzero/src/IceInstX86BaseImpl.h - Generic X86 instructions -*- C++ -*=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1248 matching lines @@
     Str << "\t"
            "cwtd";
     break;
   case IceType_i32:
     assert(SrcReg == InstX86Base<Machine>::Traits::RegisterSet::Reg_eax);
     assert(DestReg == InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
     Str << "\t"
            "cltd";
     break;
   case IceType_i64:
-    assert(DestReg == InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
+    assert(InstX86Base<Machine>::Traits::Is64Bit);
+    assert(SrcReg == InstX86Base<Machine>::Traits::getRaxOrDie());
+    assert(DestReg == InstX86Base<Machine>::Traits::getRdxOrDie());
     Str << "\t"
-           "cdto";
+           "cqo";
     break;
   }
 }
 
 template <class Machine>
 void InstX86Cbwdq<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 1);
   Operand *Src0 = this->getSrc(0);
@@ skipping 840 matching lines @@
     // acceptable type.
     Src0Var->asType(isVectorType(Ty) ? IceType_i32 : Ty, Variable::NoRegister)
         ->emit(Func);
   } else {
     Src0->emit(Func);
   }
   Str << ", ";
   this->getDest()->emit(Func);
 }
 
-inline bool isIntegerConstant(const Operand *Op) {
-  return llvm::isa<ConstantInteger32>(Op) || llvm::isa<ConstantInteger64>(Op);
-}
-
 template <class Machine> void InstX86Mov<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   Operand *Src = this->getSrc(0);
   Type SrcTy = Src->getType();
   Type DestTy = this->getDest()->getType();
   if (InstX86Base<Machine>::Traits::Is64Bit && DestTy == IceType_i64 &&
-      isIntegerConstant(Src)) {
+      llvm::isa<ConstantInteger64>(Src)) {
     Str << "\t"
-           "movabs\t";
+           "movabs"
+           "\t";
   } else {
     Str << "\t"
            "mov" << (!isScalarFloatingType(DestTy)
                          ? this->getWidthString(DestTy)
                          : InstX86Base<Machine>::Traits::TypeAttributes[DestTy]
                                .SdSsString) << "\t";
   }
   // For an integer truncation operation, src is wider than dest. In this case,
   // we use a mov instruction whose data width matches the narrower dest.
   // TODO: This assert disallows usages such as copying a floating
@@ skipping 49 matching lines @@
   assert(Target->typeWidthInBytesOnStack(this->getDest()->getType()) ==
          Target->typeWidthInBytesOnStack(Src->getType()));
   if (Dest->hasReg()) {
     if (isScalarFloatingType(DestTy)) {
       emitIASRegOpTyXMM<Machine>(Func, DestTy, Dest, Src, XmmRegEmitter);
       return;
     } else {
       assert(isScalarIntegerType(DestTy));
       // Widen DestTy for truncation (see above note). We should only do this
       // when both Src and Dest are integer types.
-      if (InstX86Base<Machine>::Traits::Is64Bit && DestTy == IceType_i64 &&
-          isIntegerConstant(Src)) {
-        uint64_t Value = -1;
+      if (InstX86Base<Machine>::Traits::Is64Bit && DestTy == IceType_i64) {
         if (const auto *C64 = llvm::dyn_cast<ConstantInteger64>(Src)) {
-          Value = C64->getValue();
-        } else {
-          Value = llvm::cast<ConstantInteger32>(Src)->getValue();
+          Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>()
+              ->movabs(InstX86Base<Machine>::Traits::getEncodedGPR(
+                           Dest->getRegNum()),
+                       C64->getValue());
+          return;
         }
-        Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>()
-            ->movabs(
-                InstX86Base<Machine>::Traits::getEncodedGPR(Dest->getRegNum()),
-                Value);
-        return;
       }
       if (isScalarIntegerType(SrcTy)) {
         SrcTy = DestTy;
       }
       emitIASRegOpTyGPR<Machine>(Func, DestTy, Dest, Src, GPRRegEmitter);
       return;
     }
   } else {
     // Dest must be Stack and Src *could* be a register. Use Src's type to
     // decide on the emitters.
@@ skipping 13 matching lines @@
       // Src can be a register or immediate.
       assert(isScalarIntegerType(SrcTy));
       emitIASAddrOpTyGPR<Machine>(Func, SrcTy, StackAddr, Src, GPRAddrEmitter);
       return;
     }
     return;
   }
 }
 
 template <class Machine>
+void InstX86Movd<Machine>::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  assert(this->getSrcSize() == 1);
+  Variable *Dest = this->getDest();
+  Operand *Src = this->getSrc(0);
+
+  if (Dest->getType() == IceType_i64 || Src->getType() == IceType_i64) {
+    assert(Dest->getType() == IceType_f64 || Src->getType() == IceType_f64);
+    assert(Dest->getType() != Src->getType());
+    Ostream &Str = Func->getContext()->getStrEmit();
+    Str << "\t"
+           "movq"
+           "\t";
+    Src->emit(Func);
+    Str << ", ";
+    Dest->emit(Func);
+    return;
+  }
+
+  InstX86BaseUnaryopXmm<Machine, InstX86Base<Machine>::Movd>::emit(Func);
+}
+
+template <class Machine>
 void InstX86Movd<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 1);
   const Variable *Dest = this->getDest();
   auto *Target = InstX86Base<Machine>::getTarget(Func);
   // For insert/extract element (one of Src/Dest is an Xmm vector and the other
   // is an int type).
   if (const auto *SrcVar = llvm::dyn_cast<Variable>(this->getSrc(0))) {
     if (SrcVar->getType() == IceType_i32 ||
@@ skipping 79 matching lines @@
 
 template <class Machine>
 void InstX86Movq<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   assert(this->getDest()->getType() == IceType_i64 ||
          this->getDest()->getType() == IceType_f64);
   Str << "\t"
-         "movq\t";
+         "movq"
+         "\t";
   this->getSrc(0)->emit(Func);
   Str << ", ";
   this->getDest()->emit(Func);
 }
 
 template <class Machine>
 void InstX86Movq<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 1);
   assert(this->getDest()->getType() == IceType_i64 ||
          this->getDest()->getType() == IceType_f64);
@@ skipping 32 matching lines @@
   // use the full register for Dest to avoid having an OperandSizeOverride
   // prefix. It also allows us to only dispatch on SrcTy.
   Type SrcTy = Src->getType();
   assert(typeWidthInBytes(Dest->getType()) > 1);
   assert(typeWidthInBytes(Dest->getType()) > typeWidthInBytes(SrcTy));
   emitIASRegOpTyGPR<Machine, false, true>(Func, SrcTy, Dest, Src,
                                           this->Emitter);
 }
 
 template <class Machine>
+void InstX86Movzx<Machine>::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  if (InstX86Base<Machine>::Traits::Is64Bit) {
+    // There's no movzx %eXX, %rXX. To zero extend 32- to 64-bits, we emit a
+    // mov %eXX, %eXX. The processor will still do a movzx[bw]q.
+    assert(this->getSrcSize() == 1);
+    const Operand *Src = this->getSrc(0);
+    const Variable *Dest = this->Dest;
+    if (Src->getType() == IceType_i32 && Dest->getType() == IceType_i64) {
+      Ostream &Str = Func->getContext()->getStrEmit();
+      Str << "\t"
+             "mov"
+             "\t";
+      Src->emit(Func);
+      Str << ", ";
+      Dest->asType(IceType_i32, InstX86Base<Machine>::Traits::getGprForType(
+                                    IceType_i32, Dest->getRegNum()))
+          ->emit(Func);
+      Str << " /* movzx */";
+      return;
+    }
+  }
+  InstX86BaseUnaryopGPR<Machine, InstX86Base<Machine>::Movzx>::emit(Func);
+}
+
+template <class Machine>
 void InstX86Movzx<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 1);
   const Variable *Dest = this->getDest();
   const Operand *Src = this->getSrc(0);
   Type SrcTy = Src->getType();
   assert(typeWidthInBytes(Dest->getType()) > 1);
   assert(typeWidthInBytes(Dest->getType()) > typeWidthInBytes(SrcTy));
   emitIASRegOpTyGPR<Machine, false, true>(Func, SrcTy, Dest, Src,
                                           this->Emitter);
 }
@@ skipping 609 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "IACA_END";
 }
 
 } // end of namespace X86Internal
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTX86BASEIMPL_H