Subzero. X8664. Fixes filetype=asm.

src/IceTargetLoweringX8664.cpp

 //===- subzero/src/IceTargetLoweringX8664.cpp - x86-64 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 100 matching lines @@
 //------------------------------------------------------------------------------
 namespace {
 static inline TargetX8664::Traits::RegisterSet::AllRegisters
 getRegisterForXmmArgNum(uint32_t ArgNum) {
   assert(ArgNum < TargetX8664::Traits::X86_MAX_XMM_ARGS);
   return static_cast<TargetX8664::Traits::RegisterSet::AllRegisters>(
       TargetX8664::Traits::RegisterSet::Reg_xmm0 + ArgNum);
 }
 
 static inline TargetX8664::Traits::RegisterSet::AllRegisters
-getRegisterForGprArgNum(uint32_t ArgNum) {
+getRegisterForGprArgNum(Type Ty, uint32_t ArgNum) {
   assert(ArgNum < TargetX8664::Traits::X86_MAX_GPR_ARGS);
   static const TargetX8664::Traits::RegisterSet::AllRegisters GprForArgNum[] = {
-      TargetX8664::Traits::RegisterSet::Reg_edi,
-      TargetX8664::Traits::RegisterSet::Reg_esi,
-      TargetX8664::Traits::RegisterSet::Reg_edx,
-      TargetX8664::Traits::RegisterSet::Reg_ecx,
-      TargetX8664::Traits::RegisterSet::Reg_r8d,
-      TargetX8664::Traits::RegisterSet::Reg_r9d,
+      TargetX8664::Traits::RegisterSet::Reg_rdi,
+      TargetX8664::Traits::RegisterSet::Reg_rsi,
+      TargetX8664::Traits::RegisterSet::Reg_rdx,
+      TargetX8664::Traits::RegisterSet::Reg_rcx,
+      TargetX8664::Traits::RegisterSet::Reg_r8,
+      TargetX8664::Traits::RegisterSet::Reg_r9,
   };
   static_assert(llvm::array_lengthof(GprForArgNum) ==
                     TargetX8664::TargetX8664::Traits::X86_MAX_GPR_ARGS,
                 "Mismatch between MAX_GPR_ARGS and GprForArgNum.");
-  return GprForArgNum[ArgNum];
+  assert(Ty == IceType_i64 || Ty == IceType_i32);
+  return static_cast<TargetX8664::Traits::RegisterSet::AllRegisters>(
+      TargetX8664::Traits::getGprForType(Ty, GprForArgNum[ArgNum]));
 }
 
 // constexprMax returns a (constexpr) max(S0, S1), and it is used for defining
 // OperandList in lowerCall. std::max() is supposed to work, but it doesn't.
 constexpr SizeT constexprMax(SizeT S0, SizeT S1) { return S0 < S1 ? S1 : S0; }
 
 } // end of anonymous namespace
 
 void TargetX8664::lowerCall(const InstCall *Instr) {
   // x86-64 calling convention:
@@ skipping 16 matching lines @@
   // multiple of 16 bytes. Other stack arguments are aligned to 8 bytes.
   //
   // This intends to match the section "Function Calling Sequence" of the
   // document "System V Application Binary Interface."
   NeedsStackAlignment = true;
 
   using OperandList =
       llvm::SmallVector<Operand *, constexprMax(Traits::X86_MAX_XMM_ARGS,
                                                 Traits::X86_MAX_GPR_ARGS)>;
   OperandList XmmArgs;
-  OperandList GprArgs;
+  CfgVector<std::pair<const Type, Operand *>> GprArgs;
   OperandList StackArgs, StackArgLocations;
   int32_t ParameterAreaSizeBytes = 0;
 
   // Classify each argument operand according to the location where the
   // argument is passed.
   for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) {
     Operand *Arg = Instr->getArg(i);
     Type Ty = Arg->getType();
     // The PNaCl ABI requires the width of arguments to be at least 32 bits.
     assert(typeWidthInBytes(Ty) >= 4);
     if (isVectorType(Ty) && XmmArgs.size() < Traits::X86_MAX_XMM_ARGS) {
       XmmArgs.push_back(Arg);
     } else if (isScalarFloatingType(Ty) &&
                XmmArgs.size() < Traits::X86_MAX_XMM_ARGS) {
       XmmArgs.push_back(Arg);
     } else if (isScalarIntegerType(Ty) &&
                GprArgs.size() < Traits::X86_MAX_GPR_ARGS) {
-      GprArgs.push_back(Arg);
+      GprArgs.emplace_back(Ty, Arg);
     } else {
       StackArgs.push_back(Arg);
       if (isVectorType(Arg->getType())) {
         ParameterAreaSizeBytes =
             Traits::applyStackAlignment(ParameterAreaSizeBytes);
       }
-      Variable *esp = getPhysicalRegister(Traits::RegisterSet::Reg_rsp);
+      Variable *esp =
+          getPhysicalRegister(Traits::RegisterSet::Reg_rsp, IceType_i64);
       Constant *Loc = Ctx->getConstantInt32(ParameterAreaSizeBytes);
       StackArgLocations.push_back(
           Traits::X86OperandMem::create(Func, Ty, esp, Loc));
       ParameterAreaSizeBytes += typeWidthInBytesOnStack(Arg->getType());
     }
   }
 
   // Adjust the parameter area so that the stack is aligned. It is assumed that
   // the stack is already aligned at the start of the calling sequence.
   ParameterAreaSizeBytes = Traits::applyStackAlignment(ParameterAreaSizeBytes);
@@ skipping 16 matching lines @@
   // done.
   for (SizeT i = 0, NumXmmArgs = XmmArgs.size(); i < NumXmmArgs; ++i) {
     Variable *Reg = legalizeToReg(XmmArgs[i], getRegisterForXmmArgNum(i));
     // Generate a FakeUse of register arguments so that they do not get dead
     // code eliminated as a result of the FakeKill of scratch registers after
     // the call.
     Context.insert<InstFakeUse>(Reg);
   }
 
   for (SizeT i = 0, NumGprArgs = GprArgs.size(); i < NumGprArgs; ++i) {
-    Variable *Reg = legalizeToReg(GprArgs[i], getRegisterForGprArgNum(i));
+    const Type SignatureTy = GprArgs[i].first;
+    Operand *Arg = GprArgs[i].second;
+    Variable *Reg =
+        legalizeToReg(Arg, getRegisterForGprArgNum(Arg->getType(), i));
+    assert(SignatureTy == IceType_i64 || SignatureTy == IceType_i32);
+    if (SignatureTy != Arg->getType()) {
+      if (SignatureTy == IceType_i32) {
+        assert(Arg->getType() == IceType_i64);
+        Variable *T = makeReg(
+            IceType_i32, Traits::getGprForType(IceType_i32, Reg->getRegNum()));
+        _mov(T, Reg);
+        Reg = T;
+      } else {
+        // This branch has never been reached, so we leave the assert(false)
+        // here until we figure out how to exercise it.
+        assert(false);
+        assert(Arg->getType() == IceType_i32);
+        Variable *T = makeReg(
+            IceType_i64, Traits::getGprForType(IceType_i64, Reg->getRegNum()));
+        _movzx(T, Reg);
+        Reg = T;
+      }
+    }
     Context.insert<InstFakeUse>(Reg);
   }
 
   // Generate the call instruction. Assign its result to a temporary with high
   // register allocation weight.
   Variable *Dest = Instr->getDest();
   // ReturnReg doubles as ReturnRegLo as necessary.
   Variable *ReturnReg = nullptr;
   if (Dest) {
     switch (Dest->getType()) {
     case IceType_NUM:
     case IceType_void:
       llvm::report_fatal_error("Invalid Call dest type");
       break;
     case IceType_i1:
     case IceType_i8:
     case IceType_i16:
+      // The bitcode should never return an i1, i8, or i16.
+      assert(false);
+    // Fallthrough intended.
     case IceType_i32:
+      ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_eax);
+      break;
     case IceType_i64:
-      ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_eax);
+      ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_rax);
       break;
     case IceType_f32:
     case IceType_f64:
     case IceType_v4i1:
     case IceType_v8i1:
     case IceType_v16i1:
     case IceType_v16i8:
     case IceType_v8i16:
     case IceType_v4i32:
     case IceType_v4f32:
       ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_xmm0);
       break;
     }
   }
 
   Operand *CallTarget = legalize(Instr->getCallTarget(), Legal_Reg | Legal_Imm);
+  if (auto *CallTargetR = llvm::dyn_cast<Variable>(CallTarget)) {
+    // x86-64 in Subzero is ILP32. Therefore, CallTarget is i32, but the emitted
+    // call needs a i64 register (for textual asm.)
+    Variable *T = makeReg(IceType_i64);
+    _movzx(T, CallTargetR);
+    CallTarget = T;
+  }
   const bool NeedSandboxing = Ctx->getFlags().getUseSandboxing();
   if (NeedSandboxing) {
     llvm_unreachable("X86-64 Sandboxing codegen not implemented.");
   }
   auto *NewCall = Context.insert<Traits::Insts::Call>(ReturnReg, CallTarget);
   if (NeedSandboxing) {
     llvm_unreachable("X86-64 Sandboxing codegen not implemented.");
   }
 
   // Insert a register-kill pseudo instruction.
@@ skipping 43 matching lines @@
       if (NumXmmArgs >= Traits::X86_MAX_XMM_ARGS) {
         continue;
       }
       RegNum = getRegisterForXmmArgNum(NumXmmArgs);
       ++NumXmmArgs;
       RegisterArg = Func->makeVariable(Ty);
     } else if (isScalarIntegerType(Ty)) {
       if (NumGprArgs >= Traits::X86_MAX_GPR_ARGS) {
         continue;
       }
-      RegNum = getRegisterForGprArgNum(NumGprArgs);
+      RegNum = getRegisterForGprArgNum(Ty, NumGprArgs);
       ++NumGprArgs;
       RegisterArg = Func->makeVariable(Ty);
     }
     assert(RegNum != Variable::NoRegister);
     assert(RegisterArg != nullptr);
     // Replace Arg in the argument list with the home register. Then generate
     // an instruction in the prolog to copy the home register to the assigned
     // location of Arg.
     if (BuildDefs::dump())
       RegisterArg->setName(Func, "home_reg:" + Arg->getName(Func));
     RegisterArg->setRegNum(RegNum);
     RegisterArg->setIsArg();
     Arg->setIsArg(false);
 
     Args[i] = RegisterArg;
     Context.insert<InstAssign>(Arg, RegisterArg);
   }
 }
 
 void TargetX8664::lowerRet(const InstRet *Inst) {
   Variable *Reg = nullptr;
   if (Inst->hasRetValue()) {
     Operand *Src0 = legalize(Inst->getRetValue());
     if (isVectorType(Src0->getType()) ||
         isScalarFloatingType(Src0->getType())) {
       Reg = legalizeToReg(Src0, Traits::RegisterSet::Reg_xmm0);
     } else {
       assert(isScalarIntegerType(Src0->getType()));
-      _mov(Reg, Src0, Traits::RegisterSet::Reg_eax);
+      _mov(Reg, Src0, Traits::getGprForType(Src0->getType(),
+                                            Traits::RegisterSet::Reg_rax));
     }
   }
   // Add a ret instruction even if sandboxing is enabled, because addEpilog
   // explicitly looks for a ret instruction as a marker for where to insert the
   // frame removal instructions.
   _ret(Reg);
   // Add a fake use of esp to make sure esp stays alive for the entire
   // function. Otherwise post-call esp adjustments get dead-code eliminated.
   keepEspLiveAtExit();
 }
@@ skipping 99 matching lines @@
     PreservedRegsSizeBytes += typeWidthInBytes(IceType_i64);
     _push(getPhysicalRegister(i, IceType_i64));
   }
   Ctx->statsUpdateRegistersSaved(NumCallee);
 
   // Generate "push ebp; mov ebp, esp"
   if (IsEbpBasedFrame) {
     assert((RegsUsed & getRegisterSet(RegSet_FramePointer, RegSet_None))
                .count() == 0);
     PreservedRegsSizeBytes += typeWidthInBytes(IceType_i64);
-    Variable *ebp = getPhysicalRegister(Traits::RegisterSet::Reg_rbp);
-    Variable *esp = getPhysicalRegister(Traits::RegisterSet::Reg_rsp);
+    Variable *ebp =
+        getPhysicalRegister(Traits::RegisterSet::Reg_rbp, IceType_i64);
+    Variable *esp =
+        getPhysicalRegister(Traits::RegisterSet::Reg_rsp, IceType_i64);
     _push(ebp);
     _mov(ebp, esp);
     // Keep ebp live for late-stage liveness analysis (e.g. asm-verbose mode).
     Context.insert<InstFakeUse>(ebp);
   }
 
   // Align the variables area. SpillAreaPaddingBytes is the size of the region
   // after the preserved registers and before the spill areas.
   // LocalsSlotsPaddingBytes is the amount of padding between the globals and
   // locals area if they are separate.
@@ skipping 27 matching lines @@
     SpillAreaSizeBytes += FixedAllocaSizeBytes;
   // Generate "sub esp, SpillAreaSizeBytes"
   if (SpillAreaSizeBytes) {
     _sub(getPhysicalRegister(getStackReg(), IceType_i64),
          Ctx->getConstantInt32(SpillAreaSizeBytes));
     // If the fixed allocas are aligned more than the stack frame, align the
     // stack pointer accordingly.
     if (PrologEmitsFixedAllocas &&
         FixedAllocaAlignBytes > Traits::X86_STACK_ALIGNMENT_BYTES) {
       assert(IsEbpBasedFrame);
-      _and(getPhysicalRegister(Traits::RegisterSet::Reg_rsp),
+      _and(getPhysicalRegister(Traits::RegisterSet::Reg_rsp, IceType_i64),
            Ctx->getConstantInt32(-FixedAllocaAlignBytes));
     }
   }
 
   // Account for alloca instructions with known frame offsets.
   if (!PrologEmitsFixedAllocas)
     SpillAreaSizeBytes += FixedAllocaSizeBytes;
 
   Ctx->statsUpdateFrameBytes(SpillAreaSizeBytes);
 
@@ skipping 88 matching lines @@
   if (RI == E)
     return;
 
   // Convert the reverse_iterator position into its corresponding (forward)
   // iterator position.
   InstList::iterator InsertPoint = RI.base();
   --InsertPoint;
   Context.init(Node);
   Context.setInsertPoint(InsertPoint);
 
-  Variable *esp = getPhysicalRegister(Traits::RegisterSet::Reg_rsp);
+  Variable *esp =
+      getPhysicalRegister(Traits::RegisterSet::Reg_rsp, IceType_i64);
   if (IsEbpBasedFrame) {
-    Variable *ebp = getPhysicalRegister(Traits::RegisterSet::Reg_rbp);
+    Variable *ebp =
+        getPhysicalRegister(Traits::RegisterSet::Reg_rbp, IceType_i64);
     // For late-stage liveness analysis (e.g. asm-verbose mode), adding a fake
     // use of esp before the assignment of esp=ebp keeps previous esp
     // adjustments from being dead-code eliminated.
     Context.insert<InstFakeUse>(esp);
     _mov(esp, ebp);
     _pop(ebp);
   } else {
     // add esp, SpillAreaSizeBytes
     if (SpillAreaSizeBytes)
       _add(esp, Ctx->getConstantInt32(SpillAreaSizeBytes));
@@ skipping 330 matching lines @@
 // case the high-level table has extra entries.
 #define X(tag, sizeLog2, align, elts, elty, str)                               \
   static_assert(_table1_##tag == _table2_##tag,                                \
                 "Inconsistency between ICETYPEX8664_TABLE and ICETYPE_TABLE");
 ICETYPE_TABLE
 #undef X
 } // end of namespace dummy3
 } // end of anonymous namespace
 
 } // end of namespace Ice