Add VADD instruction to the ARM integrated assembler.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 208 matching lines @@
   Inst->getSrc(1)->emit(Func);
   Str << ", ";
   Inst->getSrc(2)->emit(Func);
 }
 
 template <InstARM32::InstKindARM32 K>
 void InstARM32FourAddrGPR<K>::emitIAS(const Cfg *Func) const {
   emitUsingTextFixup(Func);
 }
 
+template <InstARM32::InstKindARM32 K>
+void InstARM32ThreeAddrFP<K>::emitIAS(const Cfg *Func) const {
+  emitUsingTextFixup(Func);
+}
+
 template <> void InstARM32Mla::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 3);
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   Asm->mla(getDest(), getSrc(0), getSrc(1), getSrc(2), getPredicate());
   if (Asm->needsTextFixup())
     emitUsingTextFixup(Func);
 }
 
 template <> void InstARM32Mls::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 3);
@@ skipping 346 matching lines @@
 }
 
 template <> void InstARM32Udiv::emitIAS(const Cfg *Func) const {
   assert(!SetFlags);
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   Asm->udiv(getDest(), getSrc(0), getSrc(1), getPredicate());
   if (Asm->needsTextFixup())
     emitUsingTextFixup(Func);
 }
 
+template <> void InstARM32Vadd::emitIAS(const Cfg *Func) const {
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  const Variable *Dest = getDest();
+  switch (Dest->getType()) {
+  default:
+    // TODO(kschimpf) Figure if more cases are needed.
+    Asm->setNeedsTextFixup();
+    break;
+  case IceType_f32:
+    Asm->vadds(getDest(), getSrc(0), getSrc(1), CondARM32::AL);
+    break;
+  case IceType_f64:
+    Asm->vaddd(getDest(), getSrc(0), getSrc(1), CondARM32::AL);
+    break;
+  }
+  if (Asm->needsTextFixup())
+    emitUsingTextFixup(Func);
+}
+
 InstARM32Call::InstARM32Call(Cfg *Func, Variable *Dest, Operand *CallTarget)
     : InstARM32(Func, InstARM32::Call, 1, Dest) {
   HasSideEffects = true;
   addSource(CallTarget);
 }
 
 InstARM32Label::InstARM32Label(Cfg *Func, TargetARM32 *Target)
     : InstARM32(Func, InstARM32::Label, 0, nullptr),
       Number(Target->makeNextLabelNumber()) {}
 
@@ skipping 792 matching lines @@
 
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   const auto *Reg = llvm::cast<Variable>(Dests[0]);
   if (isScalarIntegerType(Reg->getType())) {
     // Pop GPR registers.
     SizeT IntegerCount = 0;
     ARM32::IValueT GPRegisters = 0;
     const Variable *LastDest = nullptr;
     for (const Variable *Var : Dests) {
       assert(Var->hasReg() && "pop only applies to registers");
-      int32_t Reg = RegARM32::getEncodedGPR(Var->getRegNum());
+      int32_t Reg = RegARM32::getEncodedGPReg(Var->getRegNum());
       LastDest = Var;
       GPRegisters |= (1 << Reg);
       ++IntegerCount;
     }
     switch (IntegerCount) {
     case 0:
       return;
     case 1:
       // Note: Can only apply pop register if single register is not sp.
       assert((RegARM32::Encoded_Reg_sp != LastDest->getRegNum()) &&
@@ skipping 111 matching lines @@
 
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   const auto *Reg = llvm::cast<Variable>(getSrc(0));
   if (isScalarIntegerType(Reg->getType())) {
     // Push GPR registers.
     SizeT IntegerCount = 0;
     ARM32::IValueT GPRegisters = 0;
     const Variable *LastSrc = nullptr;
     for (SizeT Index = 0; Index < getSrcSize(); ++Index) {
       const auto *Var = llvm::cast<Variable>(getSrc(Index));
-      int32_t Reg = RegARM32::getEncodedGPR(Var->getRegNum());
+      int32_t Reg = RegARM32::getEncodedGPReg(Var->getRegNum());
       assert(Reg != RegARM32::Encoded_Not_GPR);
       LastSrc = Var;
       GPRegisters |= (1 << Reg);
       ++IntegerCount;
     }
     switch (IntegerCount) {
     case 0:
       return;
     case 1: {
       // Note: Can only apply push register if single register is not sp.
@@ skipping 597 matching lines @@
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
 template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace ARM32
 } // end of namespace Ice