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| 1 //===- subzero/src/IceConditionCodesARM32.h - Condition Codes ---*- C++ -*-===// | 1 //===- subzero/src/IceConditionCodesARM32.h - Condition Codes ---*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
| (...skipping 15 matching lines...) Expand all Loading... |
| 26 CondARM32 &operator=(const CondARM32 &) = delete; | 26 CondARM32 &operator=(const CondARM32 &) = delete; |
| 27 | 27 |
| 28 public: | 28 public: |
| 29 /// An enum of codes used for conditional instructions. The enum value should | 29 /// An enum of codes used for conditional instructions. The enum value should |
| 30 /// match the value used to encode operands in binary instructions. | 30 /// match the value used to encode operands in binary instructions. |
| 31 enum Cond { | 31 enum Cond { |
| 32 #define X(tag, encode, opp, emit) tag = encode, | 32 #define X(tag, encode, opp, emit) tag = encode, |
| 33 ICEINSTARM32COND_TABLE | 33 ICEINSTARM32COND_TABLE |
| 34 #undef X | 34 #undef X |
| 35 }; | 35 }; |
| 36 |
| 37 static bool isDefined(Cond C) { return C != kNone; } |
| 36 }; | 38 }; |
| 37 | 39 |
| 38 } // end of namespace Ice | 40 } // end of namespace Ice |
| 39 | 41 |
| 40 #endif // SUBZERO_SRC_ICECONDITIONCODESARM32_H | 42 #endif // SUBZERO_SRC_ICECONDITIONCODESARM32_H |
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Chromium Code Reviews
Issue 1540653003:
Add VADD instruction to the ARM integrated assembler. (Closed)
Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master