Add VADD instruction to the ARM integrated assembler.

src/IceRegistersARM32.h

 //===- subzero/src/IceRegistersARM32.h - Register information ---*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 128 matching lines @@
   {                                                                            \
     name, encode, cc_arg, scratch, preserved, stackptr, frameptr, isGPR,       \
         isInt, isI64Pair, isFP32, isFP64, isVec128,                            \
         (SizeOf alias_init).size(), alias_init                                 \
   }                                                                            \
   ,
       REGARM32_TABLE
 #undef X
   };
 
-  static inline GPRRegister getEncodedGPR(int32_t RegNum) {
-    assert(Reg_GPR_First <= RegNum);
-    assert(RegNum <= Reg_GPR_Last);
+  static inline bool isRegisterDefined(int32_t RegNum) {

[Jim Stichnoth, 2016/01/06 18:39:14]

This function bothers me (perhaps more than it should).

In the rest of the code base (specifically thinking of lowering, register
allocation, and x86 emission), the int32_t RegNum is gotten from
Variable::getRegNum(), perhaps guarded by Variable::hasReg() or
Variable::NoRegister.  Then the emitter just uses it without any test like this
isRegisterDefined().  That makes me think that maybe there is something special
and deeper about register numbers in ARM.

But that's not true, I think.  It looks like the only use of isRegisterDefined()
is to assert that it is true.

To make that more clear, I would change this to something like:

static inline void assertRegisterDefined(int32_t RegNum) {
  assert(RegNum >= 0 && RegNum < Reg_NUM);
}

[Karl, 2016/01/07 00:00:35]

I agree that the check is an assertion, since enums GPRRegister, SRegister,
DRegister, and QRegister define an "Encoded_Not_... = -1" value. Fixing to use
assert in name.

+    return RegNum >= 0 && RegNum < Reg_NUM;
+  }
+
+  static inline bool isGPRegister(int32_t RegNum) {
+    assert(isRegisterDefined(RegNum));
+    return Table[RegNum].IsGPR;
+  }
+
+  static inline SizeT getNumGPRegs() {

[Jim Stichnoth, 2016/01/06 18:39:14]

Can these getNumRegs() functions be defined as constexpr?

[Karl, 2016/01/07 00:00:35]

Done.

+    return Reg_GPR_Last + 1 - Reg_GPR_First;
+  }
+
+  static inline GPRRegister getEncodedGPReg(int32_t RegNum) {
+    assert(isGPRegister(RegNum));
     return GPRRegister(Table[RegNum].Encoding);
   }
 
   static inline GPRRegister getI64PairFirstGPRNum(int32_t RegNum) {
-    assert(Reg_I64PAIR_First <= RegNum);
-    assert(RegNum <= Reg_I64PAIR_Last);
+    assert(isI64RegisterPair(RegNum));
     return GPRRegister(Table[RegNum].Encoding);
   }
 
   static inline GPRRegister getI64PairSecondGPRNum(int32_t RegNum) {
-    assert(Reg_I64PAIR_First <= RegNum);
-    assert(RegNum <= Reg_I64PAIR_Last);
+    assert(isI64RegisterPair(RegNum));
     return GPRRegister(Table[RegNum].Encoding + 1);
   }
 
   static inline bool isI64RegisterPair(int32_t RegNum) {
+    assert(isRegisterDefined(RegNum));
     return Table[RegNum].IsI64Pair;
   }
 
   static inline bool isEncodedSReg(int32_t RegNum) {
+    assert(isRegisterDefined(RegNum));
     return Table[RegNum].IsFP32;
   }
 
   static inline SizeT getNumSRegs() {
     return Reg_SREG_Last + 1 - Reg_SREG_First;

[Jim Stichnoth, 2016/01/06 18:39:14]

Have I mentioned that I ***REALLY*** dislike assuming that the register enum
values are in a certain order.

I see two fairly reasonable ways to handle it.  First:

static inline SizeT getNumSRegs() {
  if (Reg_SREG_Last > Reg_SREG_First)
    return Reg_SREG_Last + 1 - Reg_SREG_First;
  return Reg_SREG_First + 1 - Reg_SREG_Last;
}

The other way is a bit more complicated (x-macros) but doesn't assume that First
and Last are at the endpoints of the enum value range.  Instead, just count the
number of "1" entries in the isFP32 column of the register table:

static inline SizeT getNumSRegs() {
  return 0
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
    + (isFP32)
    REGARM32_TABLE
#undef X
  ;
}

Or for a more syntactically structured version:

static inline SizeT getNumSRegs() {
  SizeT Count = 0;
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
  Count += (isFP32);
  REGARM32_TABLE
#undef X
  return Count;
}

though I'm not sure if this would work if getNumSRegs() is a constexpr function.

This comment applies to getNumDRegs(), and is also relevant to getNumGPRegs(). 
The x-macro implementation of getNumGPRegs() would need to sum up the isGPR
column, not the isInt column.

[Karl, 2016/01/07 00:00:35]

Changed form of count functions to use REGARM32_TABLE

   }
 
   static inline SRegister getEncodedSReg(int32_t RegNum) {
-    assert(Reg_SREG_First <= RegNum);
-    assert(RegNum <= Reg_SREG_Last);
+    assert(isEncodedSReg(RegNum));
     return SRegister(Table[RegNum].Encoding);
   }
 
+  // Note: D registers are listed from largest to smallest.

[Jim Stichnoth, 2016/01/06 18:39:14]

Move this down to getNumDRegs(), assuming it's still relevant with respect to
the CL comment above.

[Karl, 2016/01/07 00:00:35]

Removed. No longer applicable.

+
+  static inline bool isEncodedDReg(int32_t RegNum) {
+    assert(isRegisterDefined(RegNum));
+    return Table[RegNum].IsFP64;
+  }
+
+  static inline SizeT getNumDRegs() {
+    return Reg_DREG_First + 1 - Reg_DREG_Last;
+  }
+
   static inline DRegister getEncodedDReg(int32_t RegNum) {
-    assert(Reg_DREG_First <= RegNum);
-    assert(RegNum <= Reg_DREG_Last);
+    assert(isEncodedDReg(RegNum));
     return DRegister(Table[RegNum].Encoding);
   }
 
+  static inline bool isEncodedQReg(int32_t RegNum) {
+    assert(isRegisterDefined(RegNum));
+    return Table[RegNum].IsVec128;
+  }
+
   static inline QRegister getEncodedQReg(int32_t RegNum) {
-    assert(Reg_QREG_First <= RegNum);
-    assert(RegNum <= Reg_QREG_Last);
+    assert(isEncodedQReg(RegNum));
     return QRegister(Table[RegNum].Encoding);
   }
 
-  static inline IceString getRegName(SizeT RegNum) {
-    assert(RegNum < Reg_NUM);
+  static inline IceString getRegName(int32_t RegNum) {
+    assert(isRegisterDefined(RegNum));
     return Table[RegNum].Name;
   }
 };
 
 // Extend enum RegClass with ARM32-specific register classes (if any).
 enum RegClassARM32 : uint8_t { RCARM32_NUM = RC_Target };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGISTERSARM32_H