Add VADD instruction to the ARM integrated assembler.

src/IceRegistersARM32.h

 //===- subzero/src/IceRegistersARM32.h - Register information ---*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 64 matching lines @@
   /// used to binary encode register operands in instructions.
   enum QRegister {
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)              \
   Encoded_##val = encode,
     REGARM32_VEC128_TABLE
 #undef X
         Encoded_Not_QReg = -1
   };
 
+  static inline SizeT getNumGPRRegs() {
+    return Reg_GPR_Last + 1 - Reg_GPR_First;
+  }
+
   static inline GPRRegister getEncodedGPR(int32_t RegNum) {
     assert(Reg_GPR_First <= RegNum);
     assert(RegNum <= Reg_GPR_Last);
     return GPRRegister(RegNum - Reg_GPR_First);
   }
 
   static inline GPRRegister getI64PairFirstGPRNum(int32_t RegNum) {
     assert(Reg_I64PAIR_First <= RegNum);
     assert(RegNum <= Reg_I64PAIR_Last);
     return GPRRegister(2 * (RegNum - Reg_I64PAIR_First + Reg_GPR_First));
@@ skipping 11 matching lines @@
 
   static inline bool isEncodedSReg(int32_t RegNum) {
     return Reg_SREG_First <= RegNum && RegNum <= Reg_SREG_Last;
   }
 
   static inline SizeT getNumSRegs() {
     return Reg_SREG_Last + 1 - Reg_SREG_First;
   }
 
   static inline SRegister getEncodedSReg(int32_t RegNum) {
-    assert(Reg_SREG_First <= RegNum);
-    assert(RegNum <= Reg_SREG_Last);
+    assert(isEncodedSReg(RegNum));
     return SRegister(RegNum - Reg_SREG_First);
   }
 
+  // Note: D registers are listed from largest to smallest.

[Jim Stichnoth, 2015/12/19 15:31:25]

We should not be assuming any ordering (including S and Q and GP regs).  In
fact, we shouldn't even assume they are contiguous.

The IceRegistersARM32.def file has a 0/1 column indicating the register's type
(IsInt, IsFP32, etc.), and also the register's encoded value.  Can these be used
instead of relying on the _First and _Last values?

[Karl, 2016/01/05 20:24:31]

If you note the functions above this one, ALL of the encoding functions assume
that each category is contiguous. So, I followed that code. However, I agree
that we have the corresponding information in the X macro to implement
getEncodedXReg methods.

For set inclusion, I'm not sure that we can use the type. For example, general
purpose registers r9, ip, sp, lr, and pc are NOT integer. Talked to jpp to fix
this (now done). Modifying code.

+
+  static inline bool isEncodedDReg(int32_t RegNum) {
+    return Reg_DREG_First >= RegNum && RegNum >= Reg_DREG_Last;
+  }
+
+  static inline SizeT getNumDRegs() {
+    return Reg_DREG_First + 1 - Reg_DREG_Last;
+  }
+
   static inline DRegister getEncodedDReg(int32_t RegNum) {
-    assert(Reg_DREG_First <= RegNum);
-    assert(RegNum <= Reg_DREG_Last);
-    return DRegister(RegNum - Reg_DREG_First);
+    assert(isEncodedDReg(RegNum));
+    return DRegister(Reg_DREG_First - RegNum);
   }
 
   static inline QRegister getEncodedQReg(int32_t RegNum) {
     assert(Reg_QREG_First <= RegNum);
     assert(RegNum <= Reg_QREG_Last);
     return QRegister(RegNum - Reg_QREG_First);
   }
 
   static const char *RegNames[];
 };
 
 // Extend enum RegClass with ARM32-specific register classes (if any).
 enum RegClassARM32 : uint8_t { RCARM32_NUM = RC_Target };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGISTERSARM32_H