Add VADD instruction to the ARM integrated assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 300 matching lines @@
 
   void udiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
             CondARM32::Cond Cond);
 
   void umull(const Operand *OpRdLo, const Operand *OpRdHi, const Operand *OpRn,
              const Operand *OpRm, CondARM32::Cond Cond);
 
   // Implements uxtb/uxth depending on type of OpSrc0.
   void uxt(const Operand *OpRd, const Operand *OpSrc0, CondARM32::Cond Cond);
 
+  void vaddd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
+             CondARM32::Cond Cond);
+
+  void vadds(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
+             CondARM32::Cond Cond);
+
   void vpop(const Variable *OpBaseReg, SizeT NumConsecRegs,
             CondARM32::Cond Cond);
 
   void vpush(const Variable *OpBaseReg, SizeT NumConsecRegs,
              CondARM32::Cond Cond);
 
   static bool classof(const Assembler *Asm) {
     return Asm->getKind() == Asm_ARM32;
   }
 
@@ skipping 131 matching lines @@
   IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst);
 
   // Returns the offset encoded in the branch instruction Inst.
   static IOffsetT decodeBranchOffset(IValueT Inst);
 
   // Implements movw/movt, generating pattern ccccxxxxxxxsiiiiddddiiiiiiiiiiii
   // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
   // iiiiiiiiiiiiiiii=Imm16.
   void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd,
                  const Operand *OpSrc, const char *MovName);
+
+  // Emit VFP instruction with 3 D registers.
+  void emitVFPddd(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd, IValueT Dn,
+                  IValueT Dm, const char *InstName);
+
+  // Emit VFP instruction with 3 S registers.
+  void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd, IValueT Sn,
+                  IValueT Sm, const char *InstName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H