Add mls instruction to the ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 1735 matching lines @@
   constexpr const char *MlaName = "mla";
   IValueT Rd = encodeRegister(OpRd, "Rd", MlaName);
   IValueT Rn = encodeRegister(OpRn, "Rn", MlaName);
   IValueT Rm = encodeRegister(OpRm, "Rm", MlaName);
   IValueT Ra = encodeRegister(OpRa, "Ra", MlaName);
   verifyRegNotPc(Rd, "Rd", MlaName);
   verifyRegNotPc(Rn, "Rn", MlaName);
   verifyRegNotPc(Rm, "Rm", MlaName);
   verifyRegNotPc(Ra, "Ra", MlaName);
   constexpr IValueT MlaOpcode = B21;
-  constexpr bool SetFlags = false;
+  constexpr bool SetFlags = true;
   // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
-  emitMulOp(Cond, MlaOpcode, Ra, Rd, Rn, Rm, SetFlags, MlaName);
+  emitMulOp(Cond, MlaOpcode, Ra, Rd, Rn, Rm, !SetFlags, MlaName);
+}
+
+void AssemblerARM32::mls(const Operand *OpRd, const Operand *OpRn,
+                         const Operand *OpRm, const Operand *OpRa,
+                         CondARM32::Cond Cond) {
+  constexpr const char *MlsName = "mls";
+  IValueT Rd = encodeRegister(OpRd, "Rd", MlsName);
+  IValueT Rn = encodeRegister(OpRn, "Rn", MlsName);
+  IValueT Rm = encodeRegister(OpRm, "Rm", MlsName);
+  IValueT Ra = encodeRegister(OpRa, "Ra", MlsName);
+  verifyRegNotPc(Rd, "Rd", MlsName);
+  verifyRegNotPc(Rn, "Rn", MlsName);
+  verifyRegNotPc(Rm, "Rm", MlsName);
+  verifyRegNotPc(Ra, "Ra", MlsName);
+  constexpr IValueT MlsOpcode = B22 | B21;
+  constexpr bool SetFlags = true;
+  // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
+  emitMulOp(Cond, MlsOpcode, Ra, Rd, Rn, Rm, !SetFlags, MlsName);
 }
 
 void AssemblerARM32::mul(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   // MUL - ARM section A8.8.114, encoding A1.
   //   mul{s}<c> <Rd>, <Rn>, <Rm>
   //
   // cccc0000000sdddd0000mmmm1001nnnn where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, and s=SetFlags.
@@ skipping 187 matching lines @@
 
 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
                          CondARM32::Cond Cond) {
   constexpr const char *UxtName = "uxt";
   constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21;
   emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice