MIPS: Fix uninitialized upper word bits for Cvt_d_uw macro.

src/mips/macro-assembler-mips.cc

Index: src/mips/macro-assembler-mips.cc
diff --git a/src/mips/macro-assembler-mips.cc b/src/mips/macro-assembler-mips.cc
index 92a2419d30ae88ba45e1ff7e5c2dd45864c914b9..1c1ea20afbdfa17e25661ef5e704bdd51a952e22 100644
--- a/src/mips/macro-assembler-mips.cc
+++ b/src/mips/macro-assembler-mips.cc
@@ -1270,6 +1270,7 @@ void MacroAssembler::Cvt_d_uw(FPURegister fd, Register rs,
   // In FP64Mode we do convertion from long.
   if (IsFp64Mode()) {
     mtc1(rs, scratch);

[ivica.bogosavljevic, 2015/12/18 15:07:56]

After mtc1, upper 32 bits of the register are unpredictable, and we needto use
Mthc1 to set them to zeros.

+    Mthc1(zero_reg, scratch);
     cvt_d_l(fd, scratch);
   } else {
     // Convert rs to a FP value in fd.