MIPS: Fix uninitialized upper word bits for Cvt_d_uw macro.

src/mips/macro-assembler-mips.cc

 
 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>  // For LONG_MIN, LONG_MAX.
 
 #if V8_TARGET_ARCH_MIPS
 
 #include "src/base/bits.h"
@@ skipping 1251 matching lines @@
     and_(at, rt, at);
     or_(rt, t8, at);
   }
 }
 
 
 void MacroAssembler::Cvt_d_uw(FPURegister fd, Register rs,
                               FPURegister scratch) {
   // In FP64Mode we do convertion from long.
   if (IsFp64Mode()) {
     mtc1(rs, scratch);

[ivica.bogosavljevic, 2015/12/18 15:07:56]

After mtc1, upper 32 bits of the register are unpredictable, and we needto use
Mthc1 to set them to zeros.

+    Mthc1(zero_reg, scratch);
     cvt_d_l(fd, scratch);
   } else {
     // Convert rs to a FP value in fd.
     DCHECK(!fd.is(scratch));
     DCHECK(!rs.is(at));
 
     Label msb_clear, conversion_done;
     // For a value which is < 2^31, regard it as a signed positve word.
     Branch(&msb_clear, ge, rs, Operand(zero_reg), USE_DELAY_SLOT);
     mtc1(rs, fd);
@@ skipping 4580 matching lines @@
   if (mag.shift > 0) sra(result, result, mag.shift);
   srl(at, dividend, 31);
   Addu(result, result, Operand(at));
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS