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Issue 1537703002: Subzero. x8664. Resurrects the Target. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Addresses comments. Created 4 years, 12 months ago
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1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===// 1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of lowered x86-64 instructions in the 10 // This file defines properties of lowered x86-64 instructions in the
(...skipping 29 matching lines...) Expand all
40 // is32To8: A 32-bit GPR truncable to 8-bit. 40 // is32To8: A 32-bit GPR truncable to 8-bit.
41 // is16To8: A 16-bit GPR truncable to 8-bit. 41 // is16To8: A 16-bit GPR truncable to 8-bit.
42 // isTrunc8Rcvr: An 8-bit GPR that a wider GPR trivially truncates to. 42 // isTrunc8Rcvr: An 8-bit GPR that a wider GPR trivially truncates to.
43 // isAhRcvr: An 8-bit GPR that register "ah" can be assigned to. 43 // isAhRcvr: An 8-bit GPR that register "ah" can be assigned to.
44 // aliases: List of register aliases, which need not include this register. 44 // aliases: List of register aliases, which need not include this register.
45 #define REGX8664_BYTEREG_TABLE \ 45 #define REGX8664_BYTEREG_TABLE \
46 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \ 46 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
47 isGPR,is64,is32,is16,is8, isXmm, \ 47 isGPR,is64,is32,is16,is8, isXmm, \
48 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \ 48 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
49 /* 8-bit registers */ \ 49 /* 8-bit registers */ \
50 X(Reg_al, 0, "al", Reg_eax, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 50 X(Reg_al, 0, "al", Reg_rax, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
51 REGLIST3(RegX8664, rax, eax, ax)) \ 51 REGLIST3(RegX8664, rax, eax, ax)) \
52 X(Reg_cl, 1, "cl", Reg_ecx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 52 X(Reg_cl, 1, "cl", Reg_rcx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
53 REGLIST3(RegX8664, rcx, ecx, cx)) \ 53 REGLIST3(RegX8664, rcx, ecx, cx)) \
54 X(Reg_dl, 2, "dl", Reg_edx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 54 X(Reg_dl, 2, "dl", Reg_rdx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
55 REGLIST3(RegX8664, rdx, edx, dx)) \ 55 REGLIST3(RegX8664, rdx, edx, dx)) \
56 X(Reg_bl, 3, "bl", Reg_ebx, 0,1,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 56 X(Reg_bl, 3, "bl", Reg_rbx, 0,1,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
57 REGLIST3(RegX8664, rbx, ebx, bx)) \ 57 REGLIST3(RegX8664, rbx, ebx, bx)) \
58 X(Reg_spl, 4, "spl", Reg_esp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \ 58 X(Reg_spl, 4, "spl", Reg_rsp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
59 REGLIST3(RegX8664, rsp, esp, sp)) \ 59 REGLIST3(RegX8664, rsp, esp, sp)) \
60 X(Reg_bpl, 5, "bpl", Reg_ebp, 0,1,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \ 60 X(Reg_bpl, 5, "bpl", Reg_rbp, 0,1,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \
61 REGLIST3(RegX8664, rbp, ebp, bp)) \ 61 REGLIST3(RegX8664, rbp, ebp, bp)) \
62 X(Reg_sil, 6, "sil", Reg_esi, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 62 X(Reg_sil, 6, "sil", Reg_rsi, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
63 REGLIST3(RegX8664, rsi, esi, si)) \ 63 REGLIST3(RegX8664, rsi, esi, si)) \
64 X(Reg_dil, 7, "dil", Reg_edi, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 64 X(Reg_dil, 7, "dil", Reg_rdi, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
65 REGLIST3(RegX8664, rdi, edi, di)) \ 65 REGLIST3(RegX8664, rdi, edi, di)) \
66 X(Reg_r8l, 8, "r8b", Reg_r8, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 66 X(Reg_r8l, 8, "r8b", Reg_r8, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
67 REGLIST3(RegX8664, r8, r8d, r8w)) \ 67 REGLIST3(RegX8664, r8, r8d, r8w)) \
68 X(Reg_r9l, 9, "r9b", Reg_r9, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 68 X(Reg_r9l, 9, "r9b", Reg_r9, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
69 REGLIST3(RegX8664, r9, r9d, r9w)) \ 69 REGLIST3(RegX8664, r9, r9d, r9w)) \
70 X(Reg_r10l, 10, "r10b", Reg_r10, 1,0,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \ 70 X(Reg_r10l, 10, "r10b", Reg_r10, 1,0,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \
71 REGLIST3(RegX8664, r10, r10d, r10w)) \ 71 REGLIST3(RegX8664, r10, r10d, r10w)) \
72 X(Reg_r11l, 11, "r11b", Reg_r11, 1,0,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \ 72 X(Reg_r11l, 11, "r11b", Reg_r11, 1,0,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \
73 REGLIST3(RegX8664, r11, r11d, r11w)) \ 73 REGLIST3(RegX8664, r11, r11d, r11w)) \
74 X(Reg_r12l, 12, "r12b", Reg_r12, 0,1,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \ 74 X(Reg_r12l, 12, "r12b", Reg_r12, 0,1,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \
75 REGLIST3(RegX8664, r12, r12d, r12w)) \ 75 REGLIST3(RegX8664, r12, r12d, r12w)) \
76 X(Reg_r13l, 13, "r13b", Reg_r13, 0,1,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \ 76 X(Reg_r13l, 13, "r13b", Reg_r13, 0,1,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \
77 REGLIST3(RegX8664, r13, r13d, r13w)) \ 77 REGLIST3(RegX8664, r13, r13d, r13w)) \
78 X(Reg_r14l, 14, "r14b", Reg_r14, 0,1,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \ 78 X(Reg_r14l, 14, "r14b", Reg_r14, 0,1,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \
79 REGLIST3(RegX8664, r14, r14d, r14w)) \ 79 REGLIST3(RegX8664, r14, r14d, r14w)) \
80 X(Reg_r15l, 15, "r15b", Reg_r15, 0,1,0,1, 0,0,0,0,1, 0, 0,0,0,1,0, \ 80 X(Reg_r15l, 15, "r15b", Reg_r15, 0,1,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \
81 REGLIST3(RegX8664, r15, r15d, r15w)) \ 81 REGLIST3(RegX8664, r15, r15d, r15w)) \
82 /* High 8-bit registers. None are allowed for register allocation. */ \ 82 /* High 8-bit registers. None are allowed for register allocation. */ \
83 X(Reg_ah, 4, "ah", Reg_eax, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 83 X(Reg_ah, 4, "ah", Reg_rax, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
84 REGLIST3(RegX8664, rax, eax, ax)) \ 84 REGLIST3(RegX8664, rax, eax, ax)) \
85 X(Reg_ch, 5, "ch", Reg_ecx, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 85 X(Reg_ch, 5, "ch", Reg_rcx, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
86 REGLIST3(RegX8664, rcx, ecx, cx)) \ 86 REGLIST3(RegX8664, rcx, ecx, cx)) \
87 X(Reg_dh, 6, "dh", Reg_edx, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 87 X(Reg_dh, 6, "dh", Reg_rdx, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
88 REGLIST3(RegX8664, rdx, edx, dx)) \ 88 REGLIST3(RegX8664, rdx, edx, dx)) \
89 X(Reg_bh, 7, "bh", Reg_ebx, 0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 89 X(Reg_bh, 7, "bh", Reg_rbx, 0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
90 REGLIST3(RegX8664, rbx, ebx, bx)) \ 90 REGLIST3(RegX8664, rbx, ebx, bx)) \
91 /* End of 8-bit register set */ 91 /* End of 8-bit register set */
92 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, 92 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
93 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, 93 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,
94 // isTrunc8Rcvr, isAhRcvr, aliases) 94 // isTrunc8Rcvr, isAhRcvr, aliases)
95 95
96 #define REGX8664_GPR_TABLE \ 96 #define REGX8664_GPR_TABLE \
97 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \ 97 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
98 isGPR,is64,is32,is16,is8, isXmm, \ 98 isGPR,is64,is32,is16,is8, isXmm, \
99 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \ 99 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
100 /* 64-bit registers */ \ 100 /* 64-bit registers */ \
101 X(Reg_rax, 0, "rax", Reg_rax, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \ 101 X(Reg_rax, 0, "rax", Reg_rax, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
102 REGLIST4(RegX8664, eax, ax, al, ah)) \ 102 REGLIST4(RegX8664, eax, ax, al, ah)) \
103 X(Reg_rcx, 1, "rcx", Reg_rcx, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \ 103 X(Reg_rcx, 1, "rcx", Reg_rcx, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
104 REGLIST4(RegX8664, ecx, cx, cl, ch)) \ 104 REGLIST4(RegX8664, ecx, cx, cl, ch)) \
105 X(Reg_rdx, 2, "rdx", Reg_rdx, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \ 105 X(Reg_rdx, 2, "rdx", Reg_rdx, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
106 REGLIST4(RegX8664, edx, dx, dl, dh)) \ 106 REGLIST4(RegX8664, edx, dx, dl, dh)) \
107 X(Reg_rbx, 3, "rbx", Reg_rbx, 0,1,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \ 107 X(Reg_rbx, 3, "rbx", Reg_rbx, 0,1,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
108 REGLIST4(RegX8664, ebx, bx, bl, bh)) \ 108 REGLIST4(RegX8664, ebx, bx, bl, bh)) \
109 X(Reg_rsp, 4, "rsp", Reg_rsp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \ 109 X(Reg_rsp, 4, "rsp", Reg_rsp, 0,0,1,0, 1,0,0,0,0, 0, 1,0,0,0,0, \
110 REGLIST3(RegX8664, esp, sp, spl)) \ 110 REGLIST3(RegX8664, esp, sp, spl)) \
111 X(Reg_rbp, 5, "rbp", Reg_rbp, 0,1,0,1, 1,1,0,0,0, 0, 0,0,0,0,0, \ 111 X(Reg_rbp, 5, "rbp", Reg_rbp, 0,1,0,1, 1,1,0,0,0, 0, 1,0,0,0,0, \
112 REGLIST3(RegX8664, ebp, bp, bpl)) \ 112 REGLIST3(RegX8664, ebp, bp, bpl)) \
113 X(Reg_rsi, 6, "rsi", Reg_rsi, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \ 113 X(Reg_rsi, 6, "rsi", Reg_rsi, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
114 REGLIST3(RegX8664, esi, si, sil)) \ 114 REGLIST3(RegX8664, esi, si, sil)) \
115 X(Reg_rdi, 7, "rdi", Reg_rdi, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \ 115 X(Reg_rdi, 7, "rdi", Reg_rdi, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
116 REGLIST3(RegX8664, edi, di, dil)) \ 116 REGLIST3(RegX8664, edi, di, dil)) \
117 X(Reg_r8, 8, "r8", Reg_r8, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \ 117 X(Reg_r8, 8, "r8", Reg_r8, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
118 REGLIST3(RegX8664, r8d, r8w, r8l)) \ 118 REGLIST3(RegX8664, r8d, r8w, r8l)) \
119 X(Reg_r9, 9, "r9", Reg_r9, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \ 119 X(Reg_r9, 9, "r9", Reg_r9, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
120 REGLIST3(RegX8664, r9d, r9w, r9l)) \ 120 REGLIST3(RegX8664, r9d, r9w, r9l)) \
121 X(Reg_r10, 10, "r10", Reg_r10, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \ 121 X(Reg_r10, 10, "r10", Reg_r10, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
122 REGLIST3(RegX8664, r10d, r10w, r10l)) \ 122 REGLIST3(RegX8664, r10d, r10w, r10l)) \
123 X(Reg_r11, 11, "r11", Reg_r11, 1,0,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \ 123 X(Reg_r11, 11, "r11", Reg_r11, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
124 REGLIST3(RegX8664, r11d, r11w, r11l)) \ 124 REGLIST3(RegX8664, r11d, r11w, r11l)) \
125 X(Reg_r12, 12, "r12", Reg_r12, 0,1,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \ 125 X(Reg_r12, 12, "r12", Reg_r12, 0,1,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
126 REGLIST3(RegX8664, r12d, r12w, r12l)) \ 126 REGLIST3(RegX8664, r12d, r12w, r12l)) \
127 X(Reg_r13, 13, "r13", Reg_r13, 0,1,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \ 127 X(Reg_r13, 13, "r13", Reg_r13, 0,1,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
128 REGLIST3(RegX8664, r13d, r13w, r13l)) \ 128 REGLIST3(RegX8664, r13d, r13w, r13l)) \
129 X(Reg_r14, 14, "r14", Reg_r14, 0,1,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \ 129 X(Reg_r14, 14, "r14", Reg_r14, 0,1,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
130 REGLIST3(RegX8664, r14d, r14w, r14l)) \ 130 REGLIST3(RegX8664, r14d, r14w, r14l)) \
131 X(Reg_r15, 15, "r15", Reg_r15, 0,1,0,0, 1,1,0,0,0, 0, 0,0,0,0,0, \ 131 X(Reg_r15, 15, "r15", Reg_r15, 0,1,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
132 REGLIST3(RegX8664, r15d, r15w, r15l)) \ 132 REGLIST3(RegX8664, r15d, r15w, r15l)) \
133 /* 32-bit registers */ \ 133 /* 32-bit registers */ \
134 X(Reg_eax, 0, "eax", Reg_eax, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 134 X(Reg_eax, 0, "eax", Reg_rax, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
135 REGLIST4(RegX8664, rax, ax, al, ah)) \ 135 REGLIST4(RegX8664, rax, ax, al, ah)) \
136 X(Reg_ecx, 1, "ecx", Reg_ecx, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 136 X(Reg_ecx, 1, "ecx", Reg_rcx, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
137 REGLIST4(RegX8664, rcx, cx, cl, ch)) \ 137 REGLIST4(RegX8664, rcx, cx, cl, ch)) \
138 X(Reg_edx, 2, "edx", Reg_edx, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 138 X(Reg_edx, 2, "edx", Reg_rdx, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
139 REGLIST4(RegX8664, rdx, dx, dl, dh)) \ 139 REGLIST4(RegX8664, rdx, dx, dl, dh)) \
140 X(Reg_ebx, 3, "ebx", Reg_ebx, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 140 X(Reg_ebx, 3, "ebx", Reg_rbx, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
141 REGLIST4(RegX8664, rbx, bx, bl, bh)) \ 141 REGLIST4(RegX8664, rbx, bx, bl, bh)) \
142 X(Reg_esp, 4, "esp", Reg_esp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \ 142 X(Reg_esp, 4, "esp", Reg_rsp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
143 REGLIST3(RegX8664, rsp, sp, spl)) \ 143 REGLIST3(RegX8664, rsp, sp, spl)) \
144 X(Reg_ebp, 5, "ebp", Reg_ebp, 0,1,0,1, 1,0,1,0,0, 0, 0,1,0,0,0, \ 144 X(Reg_ebp, 5, "ebp", Reg_rbp, 0,1,0,1, 1,0,1,0,0, 0, 0,1,0,0,0, \
145 REGLIST3(RegX8664, rbp, bp, bpl)) \ 145 REGLIST3(RegX8664, rbp, bp, bpl)) \
146 X(Reg_esi, 6, "esi", Reg_esi, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 146 X(Reg_esi, 6, "esi", Reg_rsi, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
147 REGLIST3(RegX8664, rsi, si, sil)) \ 147 REGLIST3(RegX8664, rsi, si, sil)) \
148 X(Reg_edi, 7, "edi", Reg_edi, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 148 X(Reg_edi, 7, "edi", Reg_rdi, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
149 REGLIST3(RegX8664, rdi, di, dil)) \ 149 REGLIST3(RegX8664, rdi, di, dil)) \
150 X(Reg_r8d, 8, "r8d", Reg_r8, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 150 X(Reg_r8d, 8, "r8d", Reg_r8, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
151 REGLIST3(RegX8664, r8, r8w, r8l)) \ 151 REGLIST3(RegX8664, r8, r8w, r8l)) \
152 X(Reg_r9d, 9, "r9d", Reg_r9, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 152 X(Reg_r9d, 9, "r9d", Reg_r9, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
153 REGLIST3(RegX8664, r9, r9w, r9l)) \ 153 REGLIST3(RegX8664, r9, r9w, r9l)) \
154 X(Reg_r10d, 10, "r10d", Reg_r10, 1,0,0,1, 0,0,1,0,0, 0, 0,1,0,0,0, \ 154 X(Reg_r10d, 10, "r10d", Reg_r10, 1,0,0,1, 1,0,1,0,0, 0, 0,1,0,0,0, \
155 REGLIST3(RegX8664, r10, r10w, r10l)) \ 155 REGLIST3(RegX8664, r10, r10w, r10l)) \
156 X(Reg_r11d, 11, "r11d", Reg_r11, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 156 X(Reg_r11d, 11, "r11d", Reg_r11, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
157 REGLIST3(RegX8664, r11, r11w, r11l)) \ 157 REGLIST3(RegX8664, r11, r11w, r11l)) \
158 X(Reg_r12d, 12, "r12d", Reg_r12, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 158 X(Reg_r12d, 12, "r12d", Reg_r12, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
159 REGLIST3(RegX8664, r12, r12w, r12l)) \ 159 REGLIST3(RegX8664, r12, r12w, r12l)) \
160 X(Reg_r13d, 13, "r13d", Reg_r13, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 160 X(Reg_r13d, 13, "r13d", Reg_r13, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
161 REGLIST3(RegX8664, r13, r13w, r13l)) \ 161 REGLIST3(RegX8664, r13, r13w, r13l)) \
162 X(Reg_r14d, 14, "r14d", Reg_r14, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 162 X(Reg_r14d, 14, "r14d", Reg_r14, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
163 REGLIST3(RegX8664, r14, r14w, r14l)) \ 163 REGLIST3(RegX8664, r14, r14w, r14l)) \
164 X(Reg_r15d, 15, "r15d", Reg_r15, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 164 X(Reg_r15d, 15, "r15d", Reg_r15, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
165 REGLIST3(RegX8664, r15, r15w, r15l)) \ 165 REGLIST3(RegX8664, r15, r15w, r15l)) \
166 /* 16-bit registers */ \ 166 /* 16-bit registers */ \
167 X(Reg_ax, 0, "ax", Reg_eax, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 167 X(Reg_ax, 0, "ax", Reg_rax, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
168 REGLIST4(RegX8664, rax, eax, al, ah)) \ 168 REGLIST4(RegX8664, rax, eax, al, ah)) \
169 X(Reg_cx, 1, "cx", Reg_ecx, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 169 X(Reg_cx, 1, "cx", Reg_rcx, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
170 REGLIST4(RegX8664, rcx, ecx, cl, ch)) \ 170 REGLIST4(RegX8664, rcx, ecx, cl, ch)) \
171 X(Reg_dx, 2, "dx", Reg_edx, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 171 X(Reg_dx, 2, "dx", Reg_rdx, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
172 REGLIST4(RegX8664, rdx, edx, dl, dh)) \ 172 REGLIST4(RegX8664, rdx, edx, dl, dh)) \
173 X(Reg_bx, 3, "bx", Reg_ebx, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 173 X(Reg_bx, 3, "bx", Reg_rbx, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
174 REGLIST4(RegX8664, rbx, ebx, bl, bh)) \ 174 REGLIST4(RegX8664, rbx, ebx, bl, bh)) \
175 X(Reg_sp, 4, "sp", Reg_esp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \ 175 X(Reg_sp, 4, "sp", Reg_rsp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
176 REGLIST3(RegX8664, rsp, esp, spl)) \ 176 REGLIST3(RegX8664, rsp, esp, spl)) \
177 X(Reg_bp, 5, "bp", Reg_ebp, 0,1,0,1, 1,0,0,1,0, 0, 0,0,1,0,0, \ 177 X(Reg_bp, 5, "bp", Reg_rbp, 0,1,0,1, 1,0,0,1,0, 0, 0,0,1,0,0, \
178 REGLIST3(RegX8664, rbp, ebp, bpl)) \ 178 REGLIST3(RegX8664, rbp, ebp, bpl)) \
179 X(Reg_si, 6, "si", Reg_esi, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 179 X(Reg_si, 6, "si", Reg_rsi, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
180 REGLIST3(RegX8664, rsi, esi, sil)) \ 180 REGLIST3(RegX8664, rsi, esi, sil)) \
181 X(Reg_di, 7, "di", Reg_edi, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 181 X(Reg_di, 7, "di", Reg_rdi, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
182 REGLIST3(RegX8664, rdi, edi, dil)) \ 182 REGLIST3(RegX8664, rdi, edi, dil)) \
183 X(Reg_r8w, 8, "r8w", Reg_r8, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 183 X(Reg_r8w, 8, "r8w", Reg_r8, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
184 REGLIST3(RegX8664, r8, r8d, r8l)) \ 184 REGLIST3(RegX8664, r8, r8d, r8l)) \
185 X(Reg_r9w, 9, "r9w", Reg_r9, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 185 X(Reg_r9w, 9, "r9w", Reg_r9, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
186 REGLIST3(RegX8664, r9, r9d, r9l)) \ 186 REGLIST3(RegX8664, r9, r9d, r9l)) \
187 X(Reg_r10w, 10, "r10w", Reg_r10, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 187 X(Reg_r10w, 10, "r10w", Reg_r10, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
188 REGLIST3(RegX8664, r10, r10d, r10l)) \ 188 REGLIST3(RegX8664, r10, r10d, r10l)) \
189 X(Reg_r11w, 11, "r11w", Reg_r11, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 189 X(Reg_r11w, 11, "r11w", Reg_r11, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
190 REGLIST3(RegX8664, r11, r11d, r11l)) \ 190 REGLIST3(RegX8664, r11, r11d, r11l)) \
191 X(Reg_r12w, 12, "r12w", Reg_r12, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 191 X(Reg_r12w, 12, "r12w", Reg_r12, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
(...skipping 112 matching lines...) Expand 10 before | Expand all | Expand 10 after
304 X(v4i1, i32, "?", "", "", "", "d", "", "") \ 304 X(v4i1, i32, "?", "", "", "", "d", "", "") \
305 X(v8i1, i16, "?", "", "", "", "w", "", "") \ 305 X(v8i1, i16, "?", "", "", "", "w", "", "") \
306 X(v16i1, i8, "?", "", "", "", "b", "", "") \ 306 X(v16i1, i8, "?", "", "", "", "b", "", "") \
307 X(v16i8, i8, "?", "", "", "", "b", "", "") \ 307 X(v16i8, i8, "?", "", "", "", "b", "", "") \
308 X(v8i16, i16, "?", "", "", "", "w", "", "") \ 308 X(v8i16, i16, "?", "", "", "", "w", "", "") \
309 X(v4i32, i32, "dq", "", "", "", "d", "", "") \ 309 X(v4i32, i32, "dq", "", "", "", "d", "", "") \
310 X(v4f32, f32, "ps", "", "ps", "ps", "d", "", "") 310 X(v4f32, f32, "ps", "", "ps", "ps", "d", "", "")
311 //#define X(tag, elementty, cvt, sdss, pdps, pack, width, fld) 311 //#define X(tag, elementty, cvt, sdss, pdps, pack, width, fld)
312 312
313 #endif // SUBZERO_SRC_ICEINSTX8664_DEF 313 #endif // SUBZERO_SRC_ICEINSTX8664_DEF
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