Subzero. x8664. Resurrects the Target.

src/IceAssemblerX86Base.h

 //===- subzero/src/IceAssemblerX86Base.h - base x86 assembler -*- C++ -*---===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 900 matching lines @@
                         typename Traits::GPRRegister shifter);
 
   using LabelVector = std::vector<Label *>;
   // A vector of pool-allocated x86 labels for CFG nodes.
   LabelVector CfgNodeLabels;
   // A vector of pool-allocated x86 labels for Local labels.
   LabelVector LocalLabels;
 
   Label *getOrCreateLabel(SizeT Number, LabelVector &Labels);
 
+  void emitAddrSizeOverridePrefix() {
+    if (!Traits::Is64Bit) {
+      return;
+    }
+    static constexpr uint8_t AddrSizeOverridePrefix = 0x67;
+    emitUint8(AddrSizeOverridePrefix);
+  }
+
+  template <typename T = Traits>
+  typename std::enable_if<!T::Is64Bit, void>::type

[Jim Stichnoth, 2015/12/21 15:48:47]

remove this

+  emitAddrSizeOverridePrefix() {}
+
   // The arith_int() methods factor out the commonality between the encodings
   // of add(), Or(), adc(), sbb(), And(), sub(), Xor(), and cmp(). The Tag
   // parameter is statically asserted to be less than 8.
   template <uint32_t Tag>
   void arith_int(Type Ty, typename Traits::GPRRegister reg,
                  const Immediate &imm);
 
   template <uint32_t Tag>
   void arith_int(Type Ty, typename Traits::GPRRegister reg0,
                  typename Traits::GPRRegister reg1);
@@ skipping 27 matching lines @@
   }
 
   template <typename RegType>
   bool is8BitRegisterRequiringRex(const Type Ty, const RegType Reg) {
     static constexpr bool IsGPR =
         std::is_same<typename std::decay<RegType>::type,
                      typename Traits::ByteRegister>::value ||
         std::is_same<typename std::decay<RegType>::type,
                      typename Traits::GPRRegister>::value;
 
+    // At this point in the assembler, we have encoded regs, so it is not
+    // possible to distinguish between the "new" low byte registers introduced
+    // in x86-64 and the legacy [abcd]h registers. Because x86, we may still see
+    // ah (div) in the assembler, so we whitelist it here.
+    //
+    // The "local" uint32_t Encoded_Reg_ah is needed because RegType is an enum
+    // that is not necessarily the same type of
+    // Traits::RegisterSet::Encoded_Reg_ah.
+    constexpr uint32_t Encoded_Reg_ah = Traits::RegisterSet::Encoded_Reg_ah;
     return IsGPR && (Reg & 0x04) != 0 && (Reg & 0x08) == 0 &&
-           isByteSizedType(Ty);
+           isByteSizedType(Ty) && (Reg != Encoded_Reg_ah);
   }
 
   // assembleAndEmitRex is used for determining which (if any) rex prefix
   // should be emitted for the current instruction. It allows different types
   // for Reg and Rm because they could be of different types (e.g., in mov[sz]x
   // instructions.) If Addr is not nullptr, then Rm is ignored, and Rex.B is
   // determined by Addr instead. TyRm is still used to determine Addr's size.
   template <typename RegType, typename RmType, typename T = Traits>
   typename std::enable_if<T::Is64Bit, void>::type
   assembleAndEmitRex(const Type TyReg, const RegType Reg, const Type TyRm,
@@ skipping 93 matching lines @@
   emitUint8(0x66);
 }
 
 } // end of namespace X86Internal
 
 } // end of namespace Ice
 
 #include "IceAssemblerX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICEASSEMBLERX86BASE_H