Subzero. x8664. Resurrects the Target.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 169 matching lines @@
 /// This generally means that its lowering sequence requires more than one
 /// conditional branch, namely 64-bit integer compares and some floating-point
 /// compares. When this is true, and there is more than one consumer, we prefer
 /// to disable the folding optimization because it minimizes branches.
 template <class MachineTraits>
 bool BoolFolding<MachineTraits>::hasComplexLowering(const Inst *Instr) {
   switch (getProducerKind(Instr)) {
   default:
     return false;
   case PK_Icmp64:
-    return true;
+    return !MachineTraits::Is64Bit;
   case PK_Fcmp:
     return MachineTraits::TableFcmp[llvm::cast<InstFcmp>(Instr)->getCondition()]
                .C2 != MachineTraits::Cond::Br_None;
   }
 }
 
 template <class MachineTraits>
 bool BoolFolding<MachineTraits>::isValidFolding(
     typename BoolFolding<MachineTraits>::BoolFoldingProducerKind ProducerKind,
     typename BoolFolding<MachineTraits>::BoolFoldingConsumerKind ConsumerKind) {
@@ skipping 558 matching lines @@
 bool TargetX86Base<Machine>::doBranchOpt(Inst *I, const CfgNode *NextNode) {
   if (auto *Br = llvm::dyn_cast<typename Traits::Insts::Br>(I)) {
     return Br->optimizeBranch(NextNode);
   }
   return false;
 }
 
 template <class Machine>
 Variable *TargetX86Base<Machine>::getPhysicalRegister(SizeT RegNum, Type Ty) {
   // Special case: never allow partial reads/writes to/from %rBP and %rSP.
-  if (RegNum == Traits::RegisterSet::Reg_esp ||
-      RegNum == Traits::RegisterSet::Reg_ebp)
+  if (RegNum == getStackReg() || RegNum == getFrameReg())
     Ty = Traits::WordType;
   if (Ty == IceType_void)
     Ty = IceType_i32;
   if (PhysicalRegisters[Ty].empty())
     PhysicalRegisters[Ty].resize(Traits::RegisterSet::Reg_NUM);
   assert(RegNum < PhysicalRegisters[Ty].size());
   Variable *Reg = PhysicalRegisters[Ty][RegNum];
   if (Reg == nullptr) {
     Reg = Func->makeVariable(Ty);
     Reg->setRegNum(RegNum);
@@ skipping 210 matching lines @@
       std::max(AlignmentParam, Traits::X86_STACK_ALIGNMENT_BYTES);
   const bool OverAligned = Alignment > Traits::X86_STACK_ALIGNMENT_BYTES;
   const bool OptM1 = Ctx->getFlags().getOptLevel() == Opt_m1;
   const bool AllocaWithKnownOffset = Inst->getKnownFrameOffset();
   const bool UseFramePointer =
       hasFramePointer() || OverAligned || !AllocaWithKnownOffset || OptM1;
 
   if (UseFramePointer)
     setHasFramePointer();
 
-  Variable *esp = getPhysicalRegister(Traits::RegisterSet::Reg_esp);
+  Variable *esp = getPhysicalRegister(getStackReg());
   if (OverAligned) {
     _and(esp, Ctx->getConstantInt32(-Alignment));
   }
 
   Variable *Dest = Inst->getDest();
   Operand *TotalSize = legalize(Inst->getSizeInBytes());
 
   if (const auto *ConstantTotalSize =
           llvm::dyn_cast<ConstantInteger32>(TotalSize)) {
     const uint32_t Value =
@@ skipping 694 matching lines @@
     _mov(T, Src0);
     if (!llvm::isa<ConstantInteger32>(Src1))
       Src1 = copyToReg8(Src1, Traits::RegisterSet::Reg_cl);
     _sar(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Udiv: {
     // div and idiv are the few arithmetic operators that do not allow
     // immediates as the operand.
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
-    uint32_t Eax = Traits::RegisterSet::Reg_eax;
-    uint32_t Edx = Traits::RegisterSet::Reg_edx;
+    uint32_t Eax;
+    uint32_t Edx;
     switch (Ty) {
     default:
-      llvm_unreachable("Bad type for udiv");
-    // fallthrough
+      llvm::report_fatal_error("Bad type for udiv");
+    case IceType_i64:
+      Eax = Traits::getRaxOrDie();
+      Edx = Traits::getRdxOrDie();
     case IceType_i32:
+      Eax = Traits::RegisterSet::Reg_eax;
+      Edx = Traits::RegisterSet::Reg_edx;
       break;
     case IceType_i16:
       Eax = Traits::RegisterSet::Reg_ax;
       Edx = Traits::RegisterSet::Reg_dx;
       break;
     case IceType_i8:
       Eax = Traits::RegisterSet::Reg_al;
       Edx = Traits::RegisterSet::Reg_ah;
       break;
     }
@@ skipping 33 matching lines @@
             _sar(T, Ctx->getConstantInt(Ty, LogDiv));
           }
           _mov(Dest, T);
           return;
         }
       }
     }
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
     switch (Ty) {
     default:
-      llvm_unreachable("Bad type for sdiv");
-    // fallthrough
+      llvm::report_fatal_error("Bad type for sdiv");
+    case IceType_i64:
+      T_edx = makeReg(Ty, Traits::getRdxOrDie());
+      _mov(T, Src0, Traits::getRaxOrDie());
+      break;
     case IceType_i32:
       T_edx = makeReg(Ty, Traits::RegisterSet::Reg_edx);
       _mov(T, Src0, Traits::RegisterSet::Reg_eax);
       break;
     case IceType_i16:
       T_edx = makeReg(Ty, Traits::RegisterSet::Reg_dx);
       _mov(T, Src0, Traits::RegisterSet::Reg_ax);
       break;
     case IceType_i8:
       T_edx = makeReg(IceType_i16, Traits::RegisterSet::Reg_ax);
       _mov(T, Src0, Traits::RegisterSet::Reg_al);
       break;
     }
     _cbwdq(T_edx, T);
     _idiv(T, Src1, T_edx);
     _mov(Dest, T);
     break;
   case InstArithmetic::Urem: {
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
-    uint32_t Eax = Traits::RegisterSet::Reg_eax;
-    uint32_t Edx = Traits::RegisterSet::Reg_edx;
+    uint32_t Eax;
+    uint32_t Edx;
     switch (Ty) {
     default:
-      llvm_unreachable("Bad type for urem");
-    // fallthrough
+      llvm::report_fatal_error("Bad type for urem");
+    case IceType_i64:
+      Eax = Traits::getRaxOrDie();
+      Edx = Traits::getRdxOrDie();
+      break;
     case IceType_i32:
+      Eax = Traits::RegisterSet::Reg_eax;
+      Edx = Traits::RegisterSet::Reg_edx;
       break;
     case IceType_i16:
       Eax = Traits::RegisterSet::Reg_ax;
       Edx = Traits::RegisterSet::Reg_dx;
       break;
     case IceType_i8:
       Eax = Traits::RegisterSet::Reg_al;
       Edx = Traits::RegisterSet::Reg_ah;
       break;
     }
@@ skipping 37 matching lines @@
           _add(T, Src0);
           _and(T, Ctx->getConstantInt(Ty, -(1 << LogDiv)));
           _sub(T, Src0);
           _neg(T);
           _mov(Dest, T);
           return;
         }
       }
     }
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
-    uint32_t Eax = Traits::RegisterSet::Reg_eax;
-    uint32_t Edx = Traits::RegisterSet::Reg_edx;
+    uint32_t Eax;
+    uint32_t Edx;
     switch (Ty) {
     default:
-      llvm_unreachable("Bad type for srem");
-    // fallthrough
+      llvm::report_fatal_error("Bad type for srem");
+    case IceType_i64:
+      Eax = Traits::getRaxOrDie();
+      Edx = Traits::getRdxOrDie();
+      break;
     case IceType_i32:
+      Eax = Traits::RegisterSet::Reg_eax;
+      Edx = Traits::RegisterSet::Reg_edx;
       break;
     case IceType_i16:
       Eax = Traits::RegisterSet::Reg_ax;
       Edx = Traits::RegisterSet::Reg_dx;
       break;
     case IceType_i8:
       Eax = Traits::RegisterSet::Reg_al;
       Edx = Traits::RegisterSet::Reg_ah;
       break;
     }
@@ skipping 945 matching lines @@
 
   _movp(Dest, T);
   eliminateNextVectorSextInstruction(Dest);
 }
 
 template <typename Machine>
 template <typename T>
 typename std::enable_if<!T::Is64Bit, void>::type
 TargetX86Base<Machine>::lowerIcmp64(const InstIcmp *Icmp,
                                     const Inst *Consumer) {
+  assert(!T::Is64Bit);

[Jim Stichnoth, 2015/12/20 19:27:38]

This assert seems completely unnecessary given the std::enable_if above.

[John, 2015/12/21 13:41:32]

Done.

   // a=icmp cond, b, c ==> cmp b,c; a=1; br cond,L1; FakeUse(a); a=0; L1:
   Operand *Src0 = legalize(Icmp->getSrc(0));
   Operand *Src1 = legalize(Icmp->getSrc(1));
   Variable *Dest = Icmp->getDest();
   InstIcmp::ICond Condition = Icmp->getCondition();
   size_t Index = static_cast<size_t>(Condition);
   assert(Index < Traits::TableIcmp64Size);
   Operand *Src0LoRM = nullptr;
   Operand *Src0HiRM = nullptr;
   // Legalize the portions of Src0 that are going to be needed.
@@ skipping 688 matching lines @@
   }
   case Intrinsics::Sqrt: {
     Operand *Src = legalize(Instr->getArg(0));
     Variable *Dest = Instr->getDest();
     Variable *T = makeReg(Dest->getType());
     _sqrtss(T, Src);
     _mov(Dest, T);
     return;
   }
   case Intrinsics::Stacksave: {
-    Variable *esp =
-        Func->getTarget()->getPhysicalRegister(Traits::RegisterSet::Reg_esp);
+    Variable *esp = Func->getTarget()->getPhysicalRegister(getStackReg());
     Variable *Dest = Instr->getDest();
     _mov(Dest, esp);
     return;
   }
   case Intrinsics::Stackrestore: {
-    Variable *esp =
-        Func->getTarget()->getPhysicalRegister(Traits::RegisterSet::Reg_esp);
+    Variable *esp = Func->getTarget()->getPhysicalRegister(getStackReg());
     _redefined(_mov(esp, Instr->getArg(0)));
     return;
   }
   case Intrinsics::Trap:
     _ud2();
     return;
   case Intrinsics::UnknownIntrinsic:
     Func->setError("Should not be lowering UnknownIntrinsic");
     return;
   }
@@ skipping 21 matching lines @@
     _cmpxchg8b(Addr, T_edx, T_eax, T_ecx, T_ebx, Locked);
     auto *DestLo = llvm::cast<Variable>(loOperand(DestPrev));
     auto *DestHi = llvm::cast<Variable>(hiOperand(DestPrev));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
   int32_t Eax;
   switch (Ty) {
   default:
-    llvm_unreachable("Bad type for cmpxchg");
-  // fallthrough
+    llvm::report_fatal_error("Bad type for cmpxchg");
+  case IceType_i64:
+    Eax = Traits::getRaxOrDie();
+    break;
   case IceType_i32:
     Eax = Traits::RegisterSet::Reg_eax;
     break;
   case IceType_i16:
     Eax = Traits::RegisterSet::Reg_ax;
     break;
   case IceType_i8:
     Eax = Traits::RegisterSet::Reg_al;
     break;
   }
@@ skipping 250 matching lines @@
     auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
     auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
   typename Traits::X86OperandMem *Addr = formMemoryOperand(Ptr, Ty);
   int32_t Eax;
   switch (Ty) {
   default:
-    llvm_unreachable("Bad type for atomicRMW");
-  // fallthrough
+    llvm::report_fatal_error("Bad type for atomicRMW");
+  case IceType_i64:
+    Eax = Traits::getRaxOrDie();
+    break;
   case IceType_i32:
     Eax = Traits::RegisterSet::Reg_eax;
     break;
   case IceType_i16:
     Eax = Traits::RegisterSet::Reg_ax;
     break;
   case IceType_i8:
     Eax = Traits::RegisterSet::Reg_al;
     break;
   }
@@ skipping 48 matching lines @@
   //
   // Similar for 64-bit, but start w/ speculating that the upper 32 bits
   // are all zero, and compute the result for that case (checking the lower
   // 32 bits). Then actually compute the result for the upper bits and
   // cmov in the result from the lower computation if the earlier speculation
   // was correct.
   //
   // Cttz, is similar, but uses bsf instead, and doesn't require the xor
   // bit position conversion, and the speculation is reversed.
   assert(Ty == IceType_i32 || Ty == IceType_i64);
-  Variable *T = makeReg(IceType_i32);
+  const Type DestTy = Traits::Is64Bit ? Dest->getType() : IceType_i32;
+  Variable *T = makeReg(DestTy);
   Operand *FirstValRM = legalize(FirstVal, Legal_Mem | Legal_Reg);
   if (Cttz) {
     _bsf(T, FirstValRM);
   } else {
     _bsr(T, FirstValRM);
   }
-  Variable *T_Dest = makeReg(IceType_i32);
-  Constant *ThirtyTwo = Ctx->getConstantInt32(32);
-  Constant *ThirtyOne = Ctx->getConstantInt32(31);
+  Variable *T_Dest = makeReg(DestTy);
+  Constant *_31 = Ctx->getConstantInt32(31);
+  Constant *_32 = Ctx->getConstantInt(DestTy, 32);
   if (Cttz) {
-    _mov(T_Dest, ThirtyTwo);
+    _mov(T_Dest, _32);
   } else {
-    Constant *SixtyThree = Ctx->getConstantInt32(63);
-    _mov(T_Dest, SixtyThree);
+    Constant *_63 = Ctx->getConstantInt(DestTy, 63);
+    _mov(T_Dest, _63);
   }
   _cmov(T_Dest, T, Traits::Cond::Br_ne);
   if (!Cttz) {
-    _xor(T_Dest, ThirtyOne);
+    _xor(T_Dest, _31);
   }
   if (Traits::Is64Bit || Ty == IceType_i32) {
     _mov(Dest, T_Dest);
     return;
   }
-  _add(T_Dest, ThirtyTwo);
+  _add(T_Dest, _32);
   auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
   auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
   // Will be using "test" on this, so we need a registerized variable.
   Variable *SecondVar = legalizeToReg(SecondVal);
   Variable *T_Dest2 = makeReg(IceType_i32);
   if (Cttz) {
     _bsf(T_Dest2, SecondVar);
   } else {
     _bsr(T_Dest2, SecondVar);
-    _xor(T_Dest2, ThirtyOne);
+    _xor(T_Dest2, _31);
   }
   _test(SecondVar, SecondVar);
   _cmov(T_Dest2, T_Dest, Traits::Cond::Br_e);
   _mov(DestLo, T_Dest2);
   _mov(DestHi, Ctx->getConstantZero(IceType_i32));
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::typedLoad(Type Ty, Variable *Dest, Variable *Base,
                                        Constant *Offset) {
@@ skipping 193 matching lines @@
 
       // TODO(ascull): is 64-bit better with vector or scalar movq?
       auto *Mem = Traits::X86OperandMem::create(Func, Ty, Base, Offset);
       if (isVectorType(Ty)) {
         assert(VecReg != nullptr);
         _storep(VecReg, Mem);
       } else if (Ty == IceType_f64) {
         assert(VecReg != nullptr);
         _storeq(VecReg, Mem);
       } else {
+        assert(Ty != IceType_i64);
         _store(Ctx->getConstantInt(Ty, SpreadValue), Mem);
       }
     };
 
     // Find the largest type that can be used and use it as much as possible in
     // reverse order. Then handle any remainder with overlapping copies. Since
     // the remainder will be at the end, there will be reduces pressure on the
     // memory unit as the access to the same memory are far apart.
     Type Ty;
     if (ValValue == 0 && CountValue >= BytesPerStoreq &&
@@ skipping 1937 matching lines @@
   Variable *Reg = Func->makeVariable(Type);
   if (RegNum == Variable::NoRegister)
     Reg->setMustHaveReg();
   else
     Reg->setRegNum(RegNum);
   return Reg;
 }
 
 template <class Machine>
 const Type TargetX86Base<Machine>::TypeForSize[] = {
-    IceType_i8, IceType_i16, IceType_i32,
-    (Traits::Is64Bit ? IceType_i64 : IceType_f64), IceType_v16i8};
+    IceType_i8, IceType_i16, IceType_i32, IceType_f64, IceType_v16i8};
 template <class Machine>
 Type TargetX86Base<Machine>::largestTypeInSize(uint32_t Size,
                                                uint32_t MaxSize) {
   assert(Size != 0);
   uint32_t TyIndex = llvm::findLastSet(Size, llvm::ZB_Undefined);
   uint32_t MaxIndex = MaxSize == NoSizeLimit
                           ? llvm::array_lengthof(TypeForSize) - 1
                           : llvm::findLastSet(MaxSize, llvm::ZB_Undefined);
   return TypeForSize[std::min(TyIndex, MaxIndex)];
 }
@@ skipping 253 matching lines @@
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H