Subzero. x8664. Resurrects the Target.

src/IceTargetLoweringX8664Traits.h

 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 49 matching lines @@
 
   enum ScaleFactor { TIMES_1 = 0, TIMES_2 = 1, TIMES_4 = 2, TIMES_8 = 3 };
 
   using GPRRegister = ::Ice::RegX8664::GPRRegister;
   using ByteRegister = ::Ice::RegX8664::ByteRegister;
   using XmmRegister = ::Ice::RegX8664::XmmRegister;
 
   using Cond = ::Ice::CondX8664;
 
   using RegisterSet = ::Ice::RegX8664;
+  static const SizeT StackPtr = RegX8664::Reg_rsp;
+  static const SizeT FramePtr = RegX8664::Reg_rbp;
   static const GPRRegister Encoded_Reg_Accumulator = RegX8664::Encoded_Reg_eax;
   static const GPRRegister Encoded_Reg_Counter = RegX8664::Encoded_Reg_ecx;
   static const FixupKind PcRelFixup = llvm::ELF::R_X86_64_PC32;
-  static const FixupKind RelFixup = llvm::ELF::R_X86_64_32S;
+  static const FixupKind RelFixup = llvm::ELF::R_X86_64_32;
 
   class Operand {
   public:
     enum RexBits {
       RexNone = 0x00,
       RexBase = 0x40,
       RexW = RexBase | (1 << 3),
       RexR = RexBase | (1 << 2),
       RexX = RexBase | (1 << 1),
       RexB = RexBase | (1 << 0),
@@ skipping 164 matching lines @@
         SetModRM(2, RegX8664::Encoded_Reg_esp);
         SetSIB(Scale, Index, Base);
         SetDisp32(Disp);
         if (Fixup)
           SetFixup(Fixup);
       }
     }
 
     /// Generate a RIP-relative address expression on x86-64.
     Address(RelocOffsetT Offset, AssemblerFixup *Fixup) {
-      SetModRM(0, RegX8664::Encoded_Reg_ebp);
+      SetModRM(0x0, RegX8664::Encoded_Reg_esp);
+
+      static constexpr ScaleFactor Scale = TIMES_1;
+      SetSIB(Scale, RegX8664::Encoded_Reg_esp, RegX8664::Encoded_Reg_ebp);
       // Use the Offset in the displacement for now. If we decide to process
       // fixups later, we'll need to patch up the emitted displacement.
       SetDisp32(Offset);
       if (Fixup)
         SetFixup(Fixup);
     }
 
     static Address ofConstPool(Assembler *Asm, const Constant *Imm) {
       // TODO(jpp): ???
       AssemblerFixup *Fixup = Asm->createFixup(RelFixup, Imm);
@@ skipping 285 matching lines @@
           if (!First)
             Str << " ";
           First = false;
           Str << getRegName(Register);
         }
         Str << "}\n";
       }
     }
   }
 
+  static int32_t getRaxOrDie() { return RegisterSet::Reg_rax; }
+
+  static int32_t getRdxOrDie() { return RegisterSet::Reg_rdx; }
+
   /// The maximum number of arguments to pass in XMM registers
   static const uint32_t X86_MAX_XMM_ARGS = 8;
   /// The maximum number of arguments to pass in GPR registers
   static const uint32_t X86_MAX_GPR_ARGS = 6;
   /// The number of bits in a byte
   static const uint32_t X86_CHAR_BIT = 8;
   /// Stack alignment. This is defined in IceTargetLoweringX8664.cpp because it
   /// is used as an argument to std::max(), and the default std::less<T> has an
   /// operator(T const&, T const&) which requires this member to have an
   /// address.
@@ skipping 268 matching lines @@
 
 } // end of namespace X86Internal
 
 namespace X8664 {
 using Traits = ::Ice::X86Internal::MachineTraits<TargetX8664>;
 } // end of namespace X8664
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H