Subzero. x8664. Resurrects the Target.

src/IceInstX86BaseImpl.h

 //===- subzero/src/IceInstX86BaseImpl.h - Generic X86 instructions -*- C++ -*=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 180 matching lines @@
   this->addSource(Source);
 }
 
 template <class Machine>
 InstX86Cmpxchg<Machine>::InstX86Cmpxchg(Cfg *Func, Operand *DestOrAddr,
                                         Variable *Eax, Variable *Desired,
                                         bool Locked)
     : InstX86BaseLockable<Machine>(Func, InstX86Base<Machine>::Cmpxchg, 3,
                                    llvm::dyn_cast<Variable>(DestOrAddr),
                                    Locked) {
-  assert(InstX86Base<Machine>::Traits::getBaseReg(Eax->getRegNum()) ==
-         InstX86Base<Machine>::Traits::RegisterSet::Reg_eax);
+  constexpr uint16_t Encoded_rAX = 0;

[Jim Stichnoth, 2015/12/20 19:27:37]

It seems odd to capitalize AX here.

Also, don't you need to cast it to void for a NOASSERT/MINIMAL build?

[John, 2015/12/21 13:41:31]

that's x86 nomenclature for a register than could be either eax or rax.

+  assert(InstX86Base<Machine>::Traits::getEncodedGPR(Eax->getRegNum()) ==
+         Encoded_rAX);
   this->addSource(DestOrAddr);
   this->addSource(Eax);
   this->addSource(Desired);
 }
 
 template <class Machine>
 InstX86Cmpxchg8b<Machine>::InstX86Cmpxchg8b(
     Cfg *Func, typename InstX86Base<Machine>::Traits::X86OperandMem *Addr,
     Variable *Edx, Variable *Eax, Variable *Ecx, Variable *Ebx, bool Locked)
     : InstX86BaseLockable<Machine>(Func, InstX86Base<Machine>::Cmpxchg, 5,
@@ skipping 1289 matching lines @@
     assert(SrcReg == InstX86Base<Machine>::Traits::RegisterSet::Reg_ax);
     assert(DestReg == InstX86Base<Machine>::Traits::RegisterSet::Reg_dx);
     Asm->cwd();
     break;
   case IceType_i32:
     assert(SrcReg == InstX86Base<Machine>::Traits::RegisterSet::Reg_eax);
     assert(DestReg == InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
     Asm->cdq();
     break;
   case IceType_i64:
-    assert(DestReg == InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
+    // assert(DestReg == InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);

[Jim Stichnoth, 2015/12/20 19:27:37]

There should be *some* assert here, right?

[John, 2015/12/21 13:41:31]

Yes and no. These asserts should be in the constructor, not here (and in every
other instruction as well.) Having the assert in the ctor allows for easier
debugability -- i.e., you know where is the offending "emission" is. For now,
the assert is back for overall team morale happiness. :)

     Asm->cqo();
     break;
   }
 }
 
 template <class Machine> void InstX86Mul<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 2);
@@ skipping 938 matching lines @@
     return;
   }
 }
 
 template <class Machine>
 void InstX86Movd<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 1);
   const Variable *Dest = this->getDest();
-  const auto *SrcVar = llvm::cast<Variable>(this->getSrc(0));
   auto *Target = InstX86Base<Machine>::getTarget(Func);
   // For insert/extract element (one of Src/Dest is an Xmm vector and the other
   // is an int type).
-  if (SrcVar->getType() == IceType_i32 ||
-      (InstX86Base<Machine>::Traits::Is64Bit &&
-       SrcVar->getType() == IceType_i64)) {
-    assert(isVectorType(Dest->getType()) ||
-           (isScalarFloatingType(Dest->getType()) &&
-            typeWidthInBytes(SrcVar->getType()) ==
-                typeWidthInBytes(Dest->getType())));
+  if (const auto *SrcVar = llvm::dyn_cast<Variable>(this->getSrc(0))) {
+    if (SrcVar->getType() == IceType_i32 ||
+        (InstX86Base<Machine>::Traits::Is64Bit &&
+         SrcVar->getType() == IceType_i64)) {
+      assert(isVectorType(Dest->getType()) ||
+             (isScalarFloatingType(Dest->getType()) &&
+              typeWidthInBytes(SrcVar->getType()) ==
+                  typeWidthInBytes(Dest->getType())));
+      assert(Dest->hasReg());
+      typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister DestReg =
+          InstX86Base<Machine>::Traits::getEncodedXmm(Dest->getRegNum());
+      if (SrcVar->hasReg()) {
+        Asm->movd(
+            SrcVar->getType(), DestReg,
+            InstX86Base<Machine>::Traits::getEncodedGPR(SrcVar->getRegNum()));
+      } else {
+        typename InstX86Base<Machine>::Traits::Address StackAddr(
+            Target->stackVarToAsmOperand(SrcVar));
+        Asm->movd(SrcVar->getType(), DestReg, StackAddr);
+      }
+    } else {
+      assert(isVectorType(SrcVar->getType()) ||
+             (isScalarFloatingType(SrcVar->getType()) &&
+              typeWidthInBytes(SrcVar->getType()) ==
+                  typeWidthInBytes(Dest->getType())));
+      assert(SrcVar->hasReg());
+      assert(Dest->getType() == IceType_i32 ||
+             (InstX86Base<Machine>::Traits::Is64Bit &&
+              Dest->getType() == IceType_i64));
+      typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister SrcReg =
+          InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum());
+      if (Dest->hasReg()) {
+        Asm->movd(Dest->getType(), InstX86Base<Machine>::Traits::getEncodedGPR(
+                                       Dest->getRegNum()),
+                  SrcReg);
+      } else {
+        typename InstX86Base<Machine>::Traits::Address StackAddr(
+            Target->stackVarToAsmOperand(Dest));
+        Asm->movd(Dest->getType(), StackAddr, SrcReg);
+      }
+    }
+  } else {
     assert(Dest->hasReg());
     typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister DestReg =
         InstX86Base<Machine>::Traits::getEncodedXmm(Dest->getRegNum());
-    if (SrcVar->hasReg()) {
-      Asm->movd(
-          SrcVar->getType(), DestReg,
-          InstX86Base<Machine>::Traits::getEncodedGPR(SrcVar->getRegNum()));
-    } else {
-      typename InstX86Base<Machine>::Traits::Address StackAddr(
-          Target->stackVarToAsmOperand(SrcVar));
-      Asm->movd(SrcVar->getType(), DestReg, StackAddr);
-    }
-  } else {
-    assert(isVectorType(SrcVar->getType()) ||
-           (isScalarFloatingType(SrcVar->getType()) &&
-            typeWidthInBytes(SrcVar->getType()) ==
-                typeWidthInBytes(Dest->getType())));
-    assert(SrcVar->hasReg());
-    assert(Dest->getType() == IceType_i32 ||
-           (InstX86Base<Machine>::Traits::Is64Bit &&
-            Dest->getType() == IceType_i64));
-    typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister SrcReg =
-        InstX86Base<Machine>::Traits::getEncodedXmm(SrcVar->getRegNum());
-    if (Dest->hasReg()) {
-      Asm->movd(Dest->getType(),
-                InstX86Base<Machine>::Traits::getEncodedGPR(Dest->getRegNum()),
-                SrcReg);
-    } else {
-      typename InstX86Base<Machine>::Traits::Address StackAddr(
-          Target->stackVarToAsmOperand(Dest));
-      Asm->movd(Dest->getType(), StackAddr, SrcReg);
-    }
+    auto *Mem =
+        llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
+            this->getSrc(0));
+    Asm->movd(Mem->getType(), DestReg, Mem->toAsmAddress(Asm, Target));
   }
 }
 
 template <class Machine>
 void InstX86Movp<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   // TODO(wala,stichnot): movups works with all vector operands, but there
   // exist other instructions (movaps, movdqa, movdqu) that may perform better,
   // depending on the data type and alignment of the operands.
@@ skipping 787 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "IACA_END";
 }
 
 } // end of namespace X86Internal
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTX86BASEIMPL_H