Refactor PUSH/POP in ARM assemblers.

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 410 matching lines @@
     Vsqrt,
     Vsub
   };
 
   static constexpr size_t InstSize = sizeof(uint32_t);
 
   static const char *getWidthString(Type Ty);
   static const char *getVecWidthString(Type Ty);
   static CondARM32::Cond getOppositeCondition(CondARM32::Cond Cond);
 
+  template <AssemblyOutputForm> void startNextAsmInst(const Cfg *Func) const;
+
   /// Called inside derived methods emit() to communicate that multiple
   /// instructions are being generated. Used by emitIAS() methods to
   /// generate textual fixups for instructions that are not yet
   /// implemented.
   void startNextInst(const Cfg *Func) const;
 
   /// Shared emit routines for common forms of instructions.
   static void emitThreeAddrFP(const char *Opcode, const InstARM32 *Inst,
                               const Cfg *Func);
   static void emitFourAddrFP(const char *Opcode, const InstARM32 *Inst,
@@ skipping 617 matching lines @@
 /// regs, but not both. In any case, the list must be sorted.
 class InstARM32Pop : public InstARM32 {
   InstARM32Pop() = delete;
   InstARM32Pop(const InstARM32Pop &) = delete;
   InstARM32Pop &operator=(const InstARM32Pop &) = delete;
 
 public:
   static InstARM32Pop *create(Cfg *Func, const VarList &Dests) {
     return new (Func->allocate<InstARM32Pop>()) InstARM32Pop(Func, Dests);
   }
-  void emit(const Cfg *Func) const override;
-  void emitIAS(const Cfg *Func) const override;
+  void emit(const Cfg *Func) const override { assemble<TextualAssembly>(Func); }
+  void emitIAS(const Cfg *Func) const override {
+    assemble<BinaryAssembly>(Func);
+  }
+  template <AssemblyOutputForm> void assemble(const Cfg *Func) const;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Pop); }
 
 private:
   InstARM32Pop(Cfg *Func, const VarList &Dests);
 
   VarList Dests;
 };
 
 /// Pushes a list of registers. Just like Pop (see above), the list may be of
 /// GPRs, or VFP "s" registers, but not both.
 class InstARM32Push : public InstARM32 {
   InstARM32Push() = delete;
   InstARM32Push(const InstARM32Push &) = delete;
   InstARM32Push &operator=(const InstARM32Push &) = delete;
 
 public:
   static InstARM32Push *create(Cfg *Func, const VarList &Srcs) {
     return new (Func->allocate<InstARM32Push>()) InstARM32Push(Func, Srcs);
   }
-  void emit(const Cfg *Func) const override;
-  void emitIAS(const Cfg *Func) const override;
+  void emit(const Cfg *Func) const override { assemble<TextualAssembly>(Func); }
+  void emitIAS(const Cfg *Func) const override {
+    assemble<BinaryAssembly>(Func);
+  }
+  template <AssemblyOutputForm> void assemble(const Cfg *Func) const;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Push); }
 
 private:
   InstARM32Push(Cfg *Func, const VarList &Srcs);
 };
 
 /// Ret pseudo-instruction. This is actually a "bx" instruction with an "lr"
 /// register operand, but epilogue lowering will search for a Ret instead of a
 /// generic "bx". This instruction also takes a Source operand (for non-void
@@ skipping 270 matching lines @@
 // default implementations. Without this, there is the possibility of ODR
 // violations and link errors.
 
 template <> void InstARM32Ldr::emit(const Cfg *Func) const;
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H