Refactor PUSH/POP in ARM assemblers.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 237 matching lines @@
   void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void mvn(const Operand *OpRd, const Operand *OpScc, CondARM32::Cond Cond);
 
   void nop();
 
   void orr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
-  void pop(const Operand *OpRt, CondARM32::Cond Cond);
+  template <AssemblyOutputForm>

[John, 2016/01/04 15:27:49]

The idea of the assembler emitting textual output is very confusing. Plus, this
feature is only available for select instructions, which makes matters even more
confusing. I would say no assembler should emit textual output.

[Karl, 2016/01/05 17:43:03]

Refactored so that textual generation is only in IceInstARM32.cpp.

+  void pop(const Cfg *Cfg, const Operand *OpRt, CondARM32::Cond Cond);
 
   // Note: Registers is a bitset, where bit n corresponds to register Rn.
-  void popList(const IValueT Registers, CondARM32::Cond Cond);
+  template <AssemblyOutputForm>
+  void popList(const Cfg *Cfg, const IValueT Registers, CondARM32::Cond Cond);
 
-  void push(const Operand *OpRt, CondARM32::Cond Cond);
+  template <AssemblyOutputForm>
+  void push(const Cfg *Func, const Operand *OpRt, CondARM32::Cond Cond);
 
   // Note: Registers is a bitset, where bit n corresponds to register Rn.
-  void pushList(const IValueT Registers, CondARM32::Cond Cond);
+  template <AssemblyOutputForm>
+  void pushList(const Cfg *Func, const IValueT Registers, CondARM32::Cond Cond);
 
   void rbit(const Operand *OpRd, const Operand *OpRm, CondARM32::Cond Cond);
 
   void rev(const Operand *OpRd, const Operand *OpRm, CondARM32::Cond Cond);
 
   void rsb(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void rsc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
@@ skipping 34 matching lines @@
 
   void udiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
             CondARM32::Cond Cond);
 
   void umull(const Operand *OpRdLo, const Operand *OpRdHi, const Operand *OpRn,
              const Operand *OpRm, CondARM32::Cond Cond);
 
   // Implements uxtb/uxth depending on type of OpSrc0.
   void uxt(const Operand *OpRd, const Operand *OpSrc0, CondARM32::Cond Cond);
 
-  void vpop(const Variable *OpBaseReg, SizeT NumConsecRegs,
+  template <AssemblyOutputForm Form>
+  void vpop(const Cfg *Func, const Variable *OpBaseReg, SizeT NumConsecRegs,
             CondARM32::Cond Cond);
 
-  void vpush(const Variable *OpBaseReg, SizeT NumConsecRegs,
+  template <AssemblyOutputForm Form>
+  void vpush(const Cfg *Func, const Variable *OpBaseReg, SizeT NumConsecRegs,
              CondARM32::Cond Cond);
 
   static bool classof(const Assembler *Asm) {
     return Asm->getKind() == Asm_ARM32;
   }
 
   void emitTextInst(const std::string &Text, SizeT InstSize);
 
 private:
   // A vector of pool-allocated x86 labels for CFG nodes.
@@ skipping 80 matching lines @@
 
   // Pattern cccc100aaaalnnnnrrrrrrrrrrrrrrrr where cccc=Cond,
   // aaaa<<21=AddressMode, l=IsLoad, nnnn=BaseReg, and
   // rrrrrrrrrrrrrrrr is bitset of Registers.
   void emitMultiMemOp(CondARM32::Cond Cond, BlockAddressMode AddressMode,
                       bool IsLoad, IValueT BaseReg, IValueT Registers,
                       const char *InstName);
 
   // Pattern ccccxxxxxDxxxxxxddddxxxxiiiiiiii where cccc=Cond, ddddD=BaseReg,
   // iiiiiiii=NumConsecRegs, and xxxxx0xxxxxx0000xxxx00000000=Opcode.
-  void emitVStackOp(CondARM32::Cond Cond, IValueT Opcode,
+  template <AssemblyOutputForm Form>
+  void emitVStackOp(const Cfg *Func, CondARM32::Cond Cond, IValueT Opcode,
                     const Variable *OpBaseReg, SizeT NumConsecRegs,
                     const char *InstName);
 
+  void emitStackTextOp(const Cfg *Func, const IValueT Registers,
+                       CondARM32::Cond Cond, const char *InstName);
+
+  void emitStackTextOp(const Cfg *Func, const Operand *OpRt,
+                       CondARM32::Cond Cond, const char *InstName);
+
   // Pattern cccc011100x1dddd1111mmmm0001nnn where cccc=Cond,
   // x=Opcode, dddd=Rd, nnnn=Rn, mmmm=Rm.
   void emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
                  IValueT Rm, const char *InstName);
 
   // Pattern ccccxxxxxxxfnnnnddddssss1001mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, ssss=Rs, f=SetFlags and xxxxxxx=Opcode.
   void emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
                  IValueT Rm, IValueT Rs, bool SetFlags, const char *InstName);
 
@@ skipping 29 matching lines @@
   // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
   // iiiiiiiiiiiiiiii=Imm16.
   void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd,
                  const Operand *OpSrc, const char *MovName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H