Refactor PUSH/POP in ARM assemblers.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 1670 matching lines @@
   //   orr{s}<c> <Rd>, <Rn>,  #<RotatedImm8>
   //
   // cccc0001100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr const char *OrrName = "orr";
   constexpr IValueT OrrOpcode = B3 | B2; // i.e. 1100
   emitType01(Cond, OrrOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags,
              OrrName);
 }
 
-void AssemblerARM32::pop(const Operand *OpRt, CondARM32::Cond Cond) {
+void AssemblerARM32::emitStackTextOp(const Cfg *Func, const IValueT Registers,
+                                     CondARM32::Cond Cond,
+                                     const char *InstName) {
+  Ostream &Str = Func->getContext()->getStrEmit();
+  Str << "\t" << InstName << Cond << "\t{";
+  bool isFirst = true;
+  for (SizeT i = 0; i < RegARM32::getNumGPRegs(); ++i) {
+    if (mask(Registers, i, 1) == 0)
+      continue;
+    if (isFirst) {
+      isFirst = false;
+    } else {
+      Str << ", ";
+    }
+    Str << RegARM32::getGPRegName(i);
+  }
+  Str << "}";
+}
+
+void AssemblerARM32::emitStackTextOp(const Cfg *Func, const Operand *OpRt,
+                                     CondARM32::Cond Cond,
+                                     const char *InstName) {
+  const IValueT Rt = encodeRegister(OpRt, "Rt", InstName);
+  const IValueT GPRegisters = 1 << Rt;
+  emitStackTextOp(Func, GPRegisters, Cond, InstName);
+}
+
+template <>
+void AssemblerARM32::pop<TextualAssembly>(const Cfg *Func, const Operand *OpRt,
+                                          CondARM32::Cond Cond) {
+  constexpr const char *Pop = "pop";
+  emitStackTextOp(Func, OpRt, Cond, Pop);
+}
+
+template <>
+void AssemblerARM32::pop<BinaryAssembly>(const Cfg *Func, const Operand *OpRt,
+                                         CondARM32::Cond Cond) {
+  (void)Func;
   // POP - ARM section A8.8.132, encoding A2:
   //   pop<c> {Rt}
   //
   // cccc010010011101dddd000000000100 where dddd=Rt and cccc=Cond.
   constexpr const char *Pop = "pop";
-  IValueT Rt = encodeRegister(OpRt, "Rt", Pop);
+  const IValueT Rt = encodeRegister(OpRt, "Rt", Pop);
   verifyRegsNotEq(Rt, "Rt", RegARM32::Encoded_Reg_sp, "sp", Pop);
   // Same as load instruction.
   constexpr bool IsLoad = true;
   constexpr bool IsByte = false;
   IValueT Address = encodeImmRegOffset(RegARM32::Encoded_Reg_sp, kWordSize,
                                        OperandARM32Mem::PostIndex);
   emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address, Pop);
 }
 
-void AssemblerARM32::popList(const IValueT Registers, CondARM32::Cond Cond) {
+template <>
+void AssemblerARM32::popList<TextualAssembly>(const Cfg *Func,
+                                              const IValueT Registers,
+                                              CondARM32::Cond Cond) {
+  constexpr const char *PopList = "pop";
+  emitStackTextOp(Func, Registers, Cond, PopList);
+}
+
+template <>
+void AssemblerARM32::popList<BinaryAssembly>(const Cfg *Func,
+                                             const IValueT Registers,
+                                             CondARM32::Cond Cond) {
+  (void)Func;
   // POP - ARM section A8.*.131, encoding A1:
   //   pop<c> <registers>
   //
   // cccc100010111101rrrrrrrrrrrrrrrr where cccc=Cond and
   // rrrrrrrrrrrrrrrr=Registers (one bit for each GP register).
   constexpr const char *PopListName = "pop {}";
   constexpr bool IsLoad = true;
   emitMultiMemOp(Cond, IA_W, IsLoad, RegARM32::Encoded_Reg_sp, Registers,
                  PopListName);
 }
 
-void AssemblerARM32::push(const Operand *OpRt, CondARM32::Cond Cond) {
+template <>
+void AssemblerARM32::push<TextualAssembly>(const Cfg *Func, const Operand *OpRt,
+                                           CondARM32::Cond Cond) {
+  constexpr const char *Push = "push";
+  emitStackTextOp(Func, OpRt, Cond, Push);
+}
+
+template <>
+void AssemblerARM32::push<BinaryAssembly>(const Cfg *Func, const Operand *OpRt,
+                                          CondARM32::Cond Cond) {
+  (void)Func;
   // PUSH - ARM section A8.8.133, encoding A2:
   //   push<c> {Rt}
   //
   // cccc010100101101dddd000000000100 where dddd=Rt and cccc=Cond.
   constexpr const char *Push = "push";
   IValueT Rt = encodeRegister(OpRt, "Rt", Push);
   verifyRegsNotEq(Rt, "Rt", RegARM32::Encoded_Reg_sp, "sp", Push);
   // Same as store instruction.
   constexpr bool isLoad = false;
   constexpr bool isByte = false;
   IValueT Address = encodeImmRegOffset(RegARM32::Encoded_Reg_sp, -kWordSize,
                                        OperandARM32Mem::PreIndex);
   emitMemOp(Cond, kInstTypeMemImmediate, isLoad, isByte, Rt, Address, Push);
 }
 
-void AssemblerARM32::pushList(const IValueT Registers, CondARM32::Cond Cond) {
+template <>
+void AssemblerARM32::pushList<TextualAssembly>(const Cfg *Func,
+                                               const IValueT Registers,
+                                               CondARM32::Cond Cond) {
+  constexpr const char *PushList = "push";
+  emitStackTextOp(Func, Registers, Cond, PushList);
+}
+
+template <>
+void AssemblerARM32::pushList<BinaryAssembly>(const Cfg *Func,
+                                              const IValueT Registers,
+                                              CondARM32::Cond Cond) {
+  (void)Func;
   // PUSH - ARM section A8.8.133, encoding A1:
   //   push<c> <Registers>
   //
   // cccc100100101101rrrrrrrrrrrrrrrr where cccc=Cond and
   // rrrrrrrrrrrrrrrr=Registers (one bit for each GP register).
   constexpr const char *PushListName = "push {}";
   constexpr bool IsLoad = false;
   emitMultiMemOp(Cond, DB_W, IsLoad, RegARM32::Encoded_Reg_sp, Registers,
                  PushListName);
 }
@@ skipping 253 matching lines @@
   emitMulOp(Cond, UmullOpcode, RdLo, RdHi, Rn, Rm, SetFlags, UmullName);
 }
 
 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
                          CondARM32::Cond Cond) {
   constexpr const char *UxtName = "uxt";
   constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21;
   emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName);
 }
 
-void AssemblerARM32::emitVStackOp(CondARM32::Cond Cond, IValueT Opcode,
-                                  const Variable *OpBaseReg,
-                                  SizeT NumConsecRegs, const char *InstName) {
+template <>
+void AssemblerARM32::emitVStackOp<TextualAssembly>(
+    const Cfg *Func, CondARM32::Cond Cond, IValueT Opcode,
+    const Variable *OpBaseReg, SizeT NumConsecRegs, const char *InstName) {
+  (void)Opcode;
+  if (!BuildDefs::dump())
+    return;
 
+  Ostream &Str = Func->getContext()->getStrEmit();
+  Str << "\t" << InstName << Cond << "\t{";
+  IValueT BaseReg = getEncodedSRegNum(OpBaseReg);
+  assert(0 < NumConsecRegs);
+  assert(NumConsecRegs <= VpushVpopMaxConsecRegs);
+  assert((BaseReg + NumConsecRegs) <= RegARM32::getNumSRegs());
+  bool isFirst = true;
+  for (SizeT i = 0; i < NumConsecRegs; ++i) {
+    if (isFirst) {
+      isFirst = false;
+    } else {
+      Str << ", ";
+    }
+    Str << RegARM32::getSRegName(BaseReg + i);
+  }
+  Str << "}";
+}
+
+template <>
+void AssemblerARM32::emitVStackOp<BinaryAssembly>(
+    const Cfg *Func, CondARM32::Cond Cond, IValueT Opcode,
+    const Variable *OpBaseReg, SizeT NumConsecRegs, const char *InstName) {
+  (void)Func;
   const IValueT BaseReg = getEncodedSRegNum(OpBaseReg);
   const IValueT DLastBit = mask(BaseReg, 0, 1); // Last bit of base register.
   const IValueT Rd = mask(BaseReg, 1, 4);       // Top 4 bits of base register.
   assert(0 < NumConsecRegs);
   assert(NumConsecRegs <= VpushVpopMaxConsecRegs);
   assert((BaseReg + NumConsecRegs) <= RegARM32::getNumSRegs());
   verifyCondDefined(Cond, InstName);
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = Opcode | (Cond << kConditionShift) | DLastBit |
                            (Rd << kRdShift) | NumConsecRegs;
   emitInst(Encoding);
 }
 
-void AssemblerARM32::vpop(const Variable *OpBaseReg, SizeT NumConsecRegs,
-                          CondARM32::Cond Cond) {
+template <AssemblyOutputForm Form>
+void AssemblerARM32::vpop(const Cfg *Func, const Variable *OpBaseReg,
+                          SizeT NumConsecRegs, CondARM32::Cond Cond) {
   // Note: Current implementation assumes that OpBaseReg is defined using S
   // registers. It doesn't implement the D register form.
   //
   // VPOP - ARM section A8.8.367, encoding A2:
   //  vpop<c> <RegList>
   //
   // cccc11001D111101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr const char *VpopName = "vpop";
   constexpr IValueT VpopOpcode =
       B27 | B26 | B23 | B21 | B20 | B19 | B18 | B16 | B11 | B9;
-  emitVStackOp(Cond, VpopOpcode, OpBaseReg, NumConsecRegs, VpopName);
+  emitVStackOp<Form>(Func, Cond, VpopOpcode, OpBaseReg, NumConsecRegs,
+                     VpopName);
 }
 
-void AssemblerARM32::vpush(const Variable *OpBaseReg, SizeT NumConsecRegs,
-                           CondARM32::Cond Cond) {
+template <AssemblyOutputForm Form>
+void AssemblerARM32::vpush(const Cfg *Func, const Variable *OpBaseReg,
+                           SizeT NumConsecRegs, CondARM32::Cond Cond) {
   // Note: Current implementation assumes that OpBaseReg is defined using S
   // registers. It doesn't implement the D register form.
   //
   // VPUSH - ARM section A8.8.368, encoding A2:
   //   vpush<c> <RegList>
   //
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr const char *VpushName = "vpush";
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
-  emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs, VpushName);
+  emitVStackOp<Form>(Func, Cond, VpushOpcode, OpBaseReg, NumConsecRegs,
+                     VpushName);
 }
 
+// Force template instantiations.
+
+template void AssemblerARM32::vpop<TextualAssembly>(const Cfg *Func,
+                                                    const Variable *OpBaseReg,
+                                                    SizeT NumConsecRegs,
+                                                    CondARM32::Cond Cond);
+
+template void AssemblerARM32::vpop<BinaryAssembly>(const Cfg *Func,
+                                                   const Variable *OpBaseReg,
+                                                   SizeT NumConsecRegs,
+                                                   CondARM32::Cond Cond);
+
+template void AssemblerARM32::vpush<TextualAssembly>(const Cfg *Func,
+                                                     const Variable *OpBaseReg,
+                                                     SizeT NumConsecRegs,
+                                                     CondARM32::Cond Cond);
+
+template void AssemblerARM32::vpush<BinaryAssembly>(const Cfg *Func,
+                                                    const Variable *OpBaseReg,
+                                                    SizeT NumConsecRegs,
+                                                    CondARM32::Cond Cond);
+
 } // end of namespace ARM32
 } // end of namespace Ice