Refactor PUSH/POP in ARM assemblers.

src/IceRegistersARM32.h

 //===- subzero/src/IceRegistersARM32.h - Register information ---*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 139 matching lines @@
     (void)RegNum;
     assert(RegNum >= 0);
     assert(RegNum < Reg_NUM);
   }
 
   static inline bool isGPRegister(int32_t RegNum) {
     assertRegisterDefined(RegNum);
     return Table[RegNum].IsGPR;
   }
 
-  static constexpr inline SizeT getNumGPRegs() {
+  static constexpr SizeT getNumGPRegs() {
     return 0
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(isGPR)
         REGARM32_TABLE
 #undef X
         ;
   }
 
-  static inline GPRRegister getEncodedGPReg(int32_t RegNum) {
+  static inline GPRRegister getEncodedGPR(int32_t RegNum) {
     assert(isGPRegister(RegNum));
     return GPRRegister(Table[RegNum].Encoding);
   }
 
+  static constexpr SizeT getNumGPRs() {
+    return 0
+#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
+          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
+  +(isGPR)
+        REGARM32_TABLE
+#undef X
+        ;
+  }
+
+  static inline bool isGPR(SizeT RegNum) {
+    assertRegisterDefined(RegNum);
+    return Table[RegNum].IsGPR;
+  }
+
+  static inline IceString getGPRName(SizeT RegNum) {
+    assert(isGPR(RegNum));
+    return Table[RegNum].Name;
+  }
+
   static inline GPRRegister getI64PairFirstGPRNum(int32_t RegNum) {
     assert(isI64RegisterPair(RegNum));
     return GPRRegister(Table[RegNum].Encoding);
   }
 
   static inline GPRRegister getI64PairSecondGPRNum(int32_t RegNum) {
     assert(isI64RegisterPair(RegNum));
     return GPRRegister(Table[RegNum].Encoding + 1);
   }
 
   static inline bool isI64RegisterPair(int32_t RegNum) {
     assertRegisterDefined(RegNum);
     return Table[RegNum].IsI64Pair;
   }
 
   static inline bool isEncodedSReg(int32_t RegNum) {
     assertRegisterDefined(RegNum);
     return Table[RegNum].IsFP32;
   }
 
-  static constexpr inline SizeT getNumSRegs() {
+  static constexpr SizeT getNumSRegs() {
     return 0
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(isFP32)
         REGARM32_TABLE
 #undef X
         ;
   }
 
+  static inline IceString getSRegName(SizeT RegNum) {
+    assert(isEncodedSReg(RegNum));
+    return Table[RegNum].Name;
+  }
+
   static inline SRegister getEncodedSReg(int32_t RegNum) {
     assert(isEncodedSReg(RegNum));
     return SRegister(Table[RegNum].Encoding);
   }
 
   static inline bool isEncodedDReg(int32_t RegNum) {
     assertRegisterDefined(RegNum);
     return Table[RegNum].IsFP64;
   }
 
@@ skipping 28 matching lines @@
   }
 };
 
 // Extend enum RegClass with ARM32-specific register classes (if any).
 enum RegClassARM32 : uint8_t { RCARM32_NUM = RC_Target };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGISTERSARM32_H