Refactor PUSH/POP in ARM assemblers.

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Declares the InstARM32 and OperandARM32 classes and their subclasses.
 ///
 /// This represents the machine instructions and operands used for ARM32 code
 /// selection.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICEINSTARM32_H
 #define SUBZERO_SRC_ICEINSTARM32_H
 
 #include "IceConditionCodesARM32.h"
 #include "IceDefs.h"
 #include "IceInst.h"
 #include "IceInstARM32.def"
 #include "IceOperand.h"
 
 namespace Ice {
 namespace ARM32 {
 
+/// Encoding of an ARM 32-bit instruction.
+using IValueT = uint32_t;
+
+/// An Offset value (+/-) used in an ARM 32-bit instruction.
+using IOffsetT = int32_t;
+
 class TargetARM32;
 
 /// OperandARM32 extends the Operand hierarchy. Its subclasses are
 /// OperandARM32Mem and OperandARM32Flex.
 class OperandARM32 : public Operand {
   OperandARM32() = delete;
   OperandARM32(const OperandARM32 &) = delete;
   OperandARM32 &operator=(const OperandARM32 &) = delete;
 
 public:
@@ skipping 317 matching lines @@
 
 /// Base class for ARM instructions. While most ARM instructions can be
 /// conditionally executed, a few of them are not predicable (halt, memory
 /// barriers, etc.).
 class InstARM32 : public InstTarget {
   InstARM32() = delete;
   InstARM32(const InstARM32 &) = delete;
   InstARM32 &operator=(const InstARM32 &) = delete;
 
 public:
+  // Defines form that assembly instruction should be synthesized.
+  enum EmitForm { Emit_Text, Emit_Binary };
+
   enum InstKindARM32 {
     k__Start = Inst::Target,
     Adc,
     Add,
     And,
     Asr,
     Bic,
     Br,
     Call,
     Clz,
@@ skipping 672 matching lines @@
   Operand *getCallTarget() const { return getSrc(0); }
   void emit(const Cfg *Func) const override;
   void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Call); }
 
 private:
   InstARM32Call(Cfg *Func, Variable *Dest, Operand *CallTarget);
 };
 
+class InstARM32RegisterStackOp : public InstARM32 {
+  InstARM32RegisterStackOp() = delete;
+  InstARM32RegisterStackOp(const InstARM32RegisterStackOp &) = delete;
+  InstARM32RegisterStackOp &
+  operator=(const InstARM32RegisterStackOp &) = delete;
+
+public:
+  void emit(const Cfg *Func) const override;
+  void emitIAS(const Cfg *Func) const override;
+  void dump(const Cfg *Func) const override;
+
+protected:
+  InstARM32RegisterStackOp(Cfg *Func, InstKindARM32 Kind, SizeT Maxsrcs,
+                           Variable *Dest)
+      : InstARM32(Func, Kind, Maxsrcs, Dest) {}
+  void emitUsingForm(const Cfg *Func, const EmitForm Form) const;
+  void emitGPRsAsText(const Cfg *Func) const;
+  void emitSRegsAsText(const Cfg *Func, const Variable *BaseReg,
+                       SizeT Regcount) const;
+  virtual const char *getDumpOpcode() const { return getGPROpcode(); }
+  virtual const char *getGPROpcode() const = 0;
+  virtual const char *getSRegOpcode() const = 0;
+  virtual Variable *getStackReg(SizeT Index) const = 0;
+  virtual SizeT getNumStackRegs() const = 0;
+  virtual void emitSingleGPR(const Cfg *Func, const EmitForm Form,
+                             const Variable *Reg) const = 0;
+  virtual void emitMultipleGPRs(const Cfg *Func, const EmitForm Form,
+                                IValueT Registers) const = 0;
+  virtual void emitSRegs(const Cfg *Func, const EmitForm Form,
+                         const Variable *BaseReg, SizeT RegCount) const = 0;
+};
+
 /// Pops a list of registers. It may be a list of GPRs, or a list of VFP "s"
 /// regs, but not both. In any case, the list must be sorted.
-class InstARM32Pop : public InstARM32 {
+class InstARM32Pop : public InstARM32RegisterStackOp {
   InstARM32Pop() = delete;
   InstARM32Pop(const InstARM32Pop &) = delete;
   InstARM32Pop &operator=(const InstARM32Pop &) = delete;
 
 public:
   static InstARM32Pop *create(Cfg *Func, const VarList &Dests) {
     return new (Func->allocate<InstARM32Pop>()) InstARM32Pop(Func, Dests);
   }
-  void emit(const Cfg *Func) const override;
-  void emitIAS(const Cfg *Func) const override;
-  void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Pop); }
 
 private:
   InstARM32Pop(Cfg *Func, const VarList &Dests);
+  virtual const char *getGPROpcode() const final;
+  virtual const char *getSRegOpcode() const final;
+  Variable *getStackReg(SizeT Index) const final;
+  SizeT getNumStackRegs() const final;
+  void emitSingleGPR(const Cfg *Func, const EmitForm Form,
+                     const Variable *Reg) const final;
+  void emitMultipleGPRs(const Cfg *Func, const EmitForm Form,
+                        IValueT Registers) const final;
+  void emitSRegs(const Cfg *Func, const EmitForm Form, const Variable *BaseReg,
+                 SizeT RegCount) const final;
 
   VarList Dests;
 };
 
 /// Pushes a list of registers. Just like Pop (see above), the list may be of
 /// GPRs, or VFP "s" registers, but not both.
-class InstARM32Push : public InstARM32 {
+class InstARM32Push : public InstARM32RegisterStackOp {
   InstARM32Push() = delete;
   InstARM32Push(const InstARM32Push &) = delete;
   InstARM32Push &operator=(const InstARM32Push &) = delete;
 
 public:
   static InstARM32Push *create(Cfg *Func, const VarList &Srcs) {
     return new (Func->allocate<InstARM32Push>()) InstARM32Push(Func, Srcs);
   }
-  void emit(const Cfg *Func) const override;
-  void emitIAS(const Cfg *Func) const override;
-  void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Push); }
 
 private:
   InstARM32Push(Cfg *Func, const VarList &Srcs);
+  const char *getGPROpcode() const final;
+  const char *getSRegOpcode() const final;
+  Variable *getStackReg(SizeT Index) const final;
+  SizeT getNumStackRegs() const final;
+  void emitSingleGPR(const Cfg *Func, const EmitForm Form,
+                     const Variable *Reg) const final;
+  void emitMultipleGPRs(const Cfg *Func, const EmitForm Form,
+                        IValueT Registers) const final;
+  void emitSRegs(const Cfg *Func, const EmitForm Form, const Variable *BaseReg,
+                 SizeT RegCount) const final;
 };
 
 /// Ret pseudo-instruction. This is actually a "bx" instruction with an "lr"
 /// register operand, but epilogue lowering will search for a Ret instead of a
 /// generic "bx". This instruction also takes a Source operand (for non-void
 /// returning functions) for liveness analysis, though a FakeUse before the ret
 /// would do just as well.
 ///
 /// NOTE: Even though "bx" can be predicated, for now leave out the predication
 /// since it's not yet known to be useful for Ret. That may complicate finding
@@ skipping 267 matching lines @@
 // violations and link errors.
 
 template <> void InstARM32Ldr::emit(const Cfg *Func) const;
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H