Refactor PUSH/POP in ARM assemblers.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 20 matching lines @@
 #include "IceConditionCodesARM32.h"
 #include "IceDefs.h"
 #include "IceFixups.h"
 #include "IceInstARM32.h"
 #include "IceRegistersARM32.h"
 #include "IceTargetLowering.h"
 
 namespace Ice {
 namespace ARM32 {
 
-/// Encoding of an ARM 32-bit instruction.
-using IValueT = uint32_t;
-
-/// An Offset value (+/-) used in an ARM 32-bit instruction.
-using IOffsetT = int32_t;
-
 /// Handles encoding of bottom/top 16 bits of an address using movw/movt.
 class MoveRelocatableFixup final : public AssemblerFixup {
   MoveRelocatableFixup &operator=(const MoveRelocatableFixup &) = delete;
   MoveRelocatableFixup(const MoveRelocatableFixup &) = default;
 
 public:
   MoveRelocatableFixup() = default;
   size_t emit(GlobalContext *Ctx, const Assembler &Asm) const final;
 };
 
@@ skipping 191 matching lines @@
   void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void mvn(const Operand *OpRd, const Operand *OpScc, CondARM32::Cond Cond);
 
   void nop();
 
   void orr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
-  void pop(const Operand *OpRt, CondARM32::Cond Cond);
+  void pop(const Variable *OpRt, CondARM32::Cond Cond);
 
   // Note: Registers is a bitset, where bit n corresponds to register Rn.
   void popList(const IValueT Registers, CondARM32::Cond Cond);
 
   void push(const Operand *OpRt, CondARM32::Cond Cond);
 
   // Note: Registers is a bitset, where bit n corresponds to register Rn.
   void pushList(const IValueT Registers, CondARM32::Cond Cond);
 
   void rbit(const Operand *OpRd, const Operand *OpRm, CondARM32::Cond Cond);
@@ skipping 201 matching lines @@
   // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
   // iiiiiiiiiiiiiiii=Imm16.
   void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd,
                  const Operand *OpSrc, const char *MovName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H